- CSB - MetaPress - Google - Bing - Yahoo
 | 2013 | |
|---|---|---|
| j36 |      | Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Shenggang Chen, Huitao Gu: Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property. Computers & Electrical Engineering 39(2): 596-612 (2013) |
| j35 | | Abdul Naeem, Axel Jantsch, Zhonghai Lu: Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 32(5): 760-773 (2013) |
| j34 | | Abbas Eslami Kiasari, Zhonghai Lu, Axel Jantsch: An Analytical Latency Model for Networks-on-Chip. IEEE Trans. VLSI Syst. 21(1): 113-123 (2013) |
| 2012 | ||
| j33 | | Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Xianju Yang: Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip. IEICE Transactions 95-D(4): 1052-1061 (2012) |
| j32 | | Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang: A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip. IEICE Transactions 95-D(5): 1519-1522 (2012) |
| j31 | | Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng: Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks. IJDSN 2012 (2012) |
| j30 | | Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch: A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications. IJERTCS 3(2): 23-39 (2012) |
| j29 | | Wenmin Hu, Zhonghai Lu, Hengzhu Liu, Axel Jantsch: TPSS: A Flexible Hardware Support for Unicast and Multicast on Network-on-Chip. JCP 7(7): 1743-1752 (2012) |
| j28 | | Jun Zhu, Ingo Sander, Axel Jantsch: Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications. ACM Trans. Embedded Comput. Syst. 11(S1): 12 (2012) |
| c117 | | Abbas Eslami Kiasari, Axel Jantsch, Marco Bekooij, Alan Burns, Zhonghai Lu: Analytical approaches for performance evaluation of networks-on-chip. CASES 2012: 211-212 |
| c116 | | Fahimeh Jafari, Axel Jantsch, Zhonghai Lu: Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling. DATE 2012: 538-541 |
| c115 | | Shaoteng Liu, Axel Jantsch, Zhonghai Lu: Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC. DATE 2012: 1289-1294 |
| c114 | | Abdul Naeem, Axel Jantsch, Zhonghai Lu: Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems. DSD 2012: 304-311 |
| c113 | | Huimin She, Zhonghai Lu, Axel Jantsch: System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost. IWCMC 2012: 549-554 |
| c112 |  | Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen: Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. PECCS 2012: 450-458 |
| 2011 | ||
| j27 | | Ming Liu, Wolfgang Kuehn, S. Lange, Shuo Yang, J. Roskoss, Zhonghai Lu, Axel Jantsch, Qiang Wang, Hao Xu, Dapeng Jin: A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments. Computing in Science and Engineering 13(2): 52-63 (2011) |
| j26 | | Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch: FPGA-Based Particle Recognition in the HADES Experiment. IEEE Design & Test of Computers 28(4): 48-57 (2011) |
| j25 | | Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Zhonghai Lu, Dimitrios Soudris, Axel Jantsch: Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations. Embedded Systems Letters 3(2): 66-69 (2011) |
| j24 | | Xiaowen Chen, Shuming Chen, Zhonghai Lu, Axel Jantsch: Hybrid Distributed Shared Memory Space in Multi-core Processors. JSW 6(12): 2369-2378 (2011) |
| c111 | | Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch: FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments. ARC 2011: 169-180 |
| c110 | | Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch: Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems. ASP-DAC 2011: 154-159 |
| c109 | | Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu: Power-efficient tree-based multicast support for Networks-on-Chip. ASP-DAC 2011: 363-368 |
| c108 | | Abdul Naeem, Axel Jantsch, Xiaowen Chen, Zhonghai Lu: Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems. DSD 2011: 47-54 |
| c107 | | Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa: Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD 2011: 310-317 |
| c106 | | Fahimeh Jafari, Axel Jantsch, Zhonghai Lu: Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling. ICCD 2011: 445-446 |
| c105 | | Chaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu, Axel Jantsch: A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip. ISVLSI 2011: 19-24 |
| c104 | | Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion: Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS 2011: 57-64 |
| c103 | | Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng: Stochastic coverage in event-driven sensor networks. PIMRC 2011: 915-919 |
| c102 | | Meganathan Deivasigamani, Shaghayeghsadat Tabatabaei, Naveed Mustafa, Hamza Ijaz, Haris Bin Aslam, Shaoteng Liu, Axel Jantsch: Concept and design of exhaustive-parallel search algorithm for Network-on-Chip. SoCC 2011: 150-155 |
| c101 | | Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang, Dongpei Liu: Network-on-Chip multicasting with low latency path setup. VLSI-SoC 2011: 290-295 |
| c100 | | Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch: 3-D integration and the limits of silicon computation. VLSI-SoC 2011: 343-348 |
| c99 | | Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng: Modeling and analysis of Rayleigh fading channels using stochastic network calculus. WCNC 2011: 1056-1061 |
| 2010 | ||
| j23 | | Radu Marculescu, Axel Jantsch: Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2009. IEEE Trans. on CAD of Integrated Circuits and Systems 29(6): 853-854 (2010) |
| j22 | | Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee: Buffer Optimization in Network-on-Chip Through Flow Regulation. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1973-1986 (2010) |
| c98 | | Jun Zhu, Ingo Sander, Axel Jantsch: Constrained global scheduling of streaming applications on MPSoCs. ASP-DAC 2010: 223-228 |
| c97 | | Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen: Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. DATE 2010: 39-44 |
| c96 | | Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch: FPGA-based adaptive computing for correlated multi-stream processing. DATE 2010: 973-976 |
| c95 | | Jun Zhu, Ingo Sander, Axel Jantsch: Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. DATE 2010: 1035-1040 |
| c94 | | Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee: Optimal regulation of traffic flows in networks-on-chip. DATE 2010: 1621-1624 |
| c93 | | Amr Helmy, Laurence Pierre, Axel Jantsch: Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing. DDECS 2010: 221-224 |
| c92 | | |
| c91 | | Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch: Scalability of weak consistency in NoC based multicore architectures. ISCAS 2010: 3497-3500 |
| c90 | | Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch: Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing. ISVLSI 2010: 80-85 |
| c89 | | Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu: Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique. ISVLSI 2010: 462-463 |
| c88 | | Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin: Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. ISVLSI 2010: 518-523 |
| c87 | | Zhipeng Chen, Axel Jantsch: A Worst Case Performance Model for TDM Virtual Circuit in NoCs. NPC 2010: 452-461 |
| c86 | | Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang: FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip. SoCC 2010: 441-446 |
| c85 | | Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen: Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory. SoCC 2010: 467-472 |
| 2009 | ||
| j21 | | Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch: Scalability of relaxed consistency models in NoC based multicore architectures. SIGARCH Computer Architecture News 37(5): 8-15 (2009) |
| p1 | | Axel Jantsch: Models of Embedded Computation for Distributed Embedded Systems. Embedded Systems Design and Verification 2009: 3 |
| c84 | | Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen: Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC 2009: 1-7 |
| c83 | | Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair C. Bruce, Pieter van der Wolf, Tomas Henriksson: Flow regulation for on-chip communication. DATE 2009: 578-581 |
| c82 | | Mikael Millberg, Axel Jantsch: Priority based forced requeue to reduce worst-case latencies for bursty traffic. DATE 2009: 1070-1075 |
| c81 | | Jun Zhu, Ingo Sander, Axel Jantsch: Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. DATE 2009: 1506-1511 |
| c80 | | Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch: Run-time Partial Reconfiguration speed investigation and architectural design space exploration. FPL 2009: 498-502 |
| c79 | | Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrholz, Philipp A. Hartmann, Wolfgang Nebel: High-level estimation and trade-off analysis for adaptive real-time systems. IPDPS 2009: 1-4 |
| c78 | | Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen: Scalability of network-on-chip communication architecture for 3-D meshes. NOCS 2009: 114-123 |
| c77 | | Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, Axel Jantsch: A Reconfigurable Design Framework for FPGA Adaptive Computing. ReConFig 2009: 439-444 |
| c76 | | Zhonghai Lu, Dimitris Brachos, Axel Jantsch: A flow regulator for On-Chip Communication. SoCC 2009: 151-154 |
| c75 | | Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng: Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks. VTC Spring 2009 |
| 2008 | ||
| j20 | | Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch: SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system. Design Autom. for Emb. Sys. 12(1-2): 1-30 (2008) |
| j19 | | Christoph Grimm, Axel Jantsch, Sandeep Kumar Shukla, Eugenio Villar: C-Based Design of Heterogeneous Embedded Systems. EURASIP J. Emb. Sys. 2008 (2008) |
| j18 | | Ingo Sander, Axel Jantsch: Modelling Adaptive Systems in ForSyDe. Electr. Notes Theor. Comput. Sci. 200(2): 39-54 (2008) |
| j17 | | Tiberiu Seceleanu, Axel Jantsch: Modeling Communication with Synchronized Environments. Fundam. Inform. 86(3): 343-369 (2008) |
| j16 | | Arseni Vitkovski, Axel Jantsch, Robert Lauter, Raimo Haukilahti, Erland Nilsson: Low-power and error protection coding for network-on-chip traffic. IET Computers & Digital Techniques 2(6): 483-492 (2008) |
| j15 | | Tarvo Raudvere, Ingo Sander, Axel Jantsch: Application and Verification of Local Nonsemantic-Preserving Transformations in System Design. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1091-1103 (2008) |
| j14 | | Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev: A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration. ACM Trans. Design Autom. Electr. Syst. 13(2) (2008) |
| j13 | | Zhonghai Lu, Axel Jantsch: TDM Virtual-Circuit Configuration for Network-on-Chip. IEEE Trans. VLSI Syst. 16(8): 1021-1034 (2008) |
| c74 | | Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel: Heterogeneous System-level Specification Using SystemC. DATE 2008 |
| c73 | | Zhonghai Lu, Lei Xia, Axel Jantsch: Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip. DDECS 2008: 92-97 |
| c72 | | Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch: System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments. DSD 2008: 599-605 |
| c71 | | Jun Zhu, Ingo Sander, Axel Jantsch: Energy efficient streaming applications with guaranteed throughput on MPSoCs. EMSOFT 2008: 119-128 |
| c70 | | Jun Zhu, Ingo Sander, Axel Jantsch: Performance analysis of reconfiguration in adaptive real-time streaming applications. ESTImedia 2008: 53-58 |
| c69 | | Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch: ATCA-based computation platform for data acquisition and triggering in particle physics experiments. FPL 2008: 287-292 |
| 2007 | ||
| j12 | | Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici: DATE 07 workshop on diagnostic services in NoCs. IEEE Design & Test of Computers 24(5): 510 (2007) |
| j11 | | Zhonghai Lu, Axel Jantsch: Admitting and ejecting flits in wormhole-switched networks on chip. IET Computers & Digital Techniques 1(5): 546-556 (2007) |
| j10 | | Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson: Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology. T. HiPEAC 1: 239-258 (2007) |
| j9 | | Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch: EWD: A metamodeling driven customizable multi-MoC system modeling framework. ACM Trans. Design Autom. Electr. Syst. 12(3) (2007) |
| c68 | | Tarvo Raudvere, Ingo Sander, Axel Jantsch: Synchronization after design refinements with sensitive delay elements. CODES+ISSS 2007: 21-26 |
| c67 | | Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luca Benini: Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions. CODES+ISSS 2007: 217-226 |
| c66 | | |
| c65 | | Mikael Millberg, Axel Jantsch: Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy. DSD 2007: 511-518 |
| c64 | | Tomas Henriksson, Pieter van der Wolf, Axel Jantsch, Alistair C. Bruce: Network Calculus Applied to Verification of Memory Access Performance in SoCs. ESTImedia 2007: 21-26 |
| c63 | | Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou: Traffic Splitting with Network Calculus for Mesh Sensor Networks. FGCN (2) 2007: 368-373 |
| c62 | | Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, Florian Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, Marcos Martínez: The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. FPL 2007: 396-401 |
| c61 | | Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez, Zhen'An Liu: Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics. FPT 2007: 177-183 |
| c60 | | Tarvo Raudvere, Ingo Sander, Axel Jantsch: A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops. ACM Great Lakes Symposium on VLSI 2007: 353-358 |
| c59 | | Zhonghai Lu, Axel Jantsch: Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip. ICCAD 2007: 18-25 |
| c58 | | Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu: Towards Open Network-on-Chip Benchmarks. NOCS 2007: 205 |
| c57 | | Per Badlund, Axel Jantsch: An Analytical Approach for Dimensioning Mixed Traffic Networks. NOCS 2007: 215 |
| c56 | | |
| c55 | | Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch: Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. IEEE International Workshop on Rapid System Prototyping 2007: 143-149 |
| 2006 | ||
| c54 | | |
| c53 | | |
| c52 | | Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson: MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis. Conf. Computing Frontiers 2006: 21-28 |
| c51 | | Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev: A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. DAC 2006: 125-130 |
| c50 | | Zhonghai Lu, Ingo Sander, Axel Jantsch: Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. DSD 2006: 37-44 |
| c49 | | Guang Liang, Axel Jantsch: Adaptive Power Management for the On-Chip Communication Network. DSD 2006: 649-656 |
| c48 | | |
| c47 | | Rikard Thid, Ingo Sander, Axel Jantsch: Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads. DSD 2006: 681-688 |
| c46 | | Zhonghai Lu, Mingchen Zhong, Axel Jantsch: Evaluation of on-chip networks using deflection routing. ACM Great Lakes Symposium on VLSI 2006: 296-301 |
| c45 | | Zhonghai Lu, Bei Yin, Axel Jantsch: Connection-oriented Multicasting in Wormhole-switched Networks on Chip. ISVLSI 2006: 205-2110 |
| c44 | | Weixing Wang, Axel Jantsch: An algorithm for electing cluster heads based on maximum residual energy. IWCMC 2006: 1465-1470 |
| c43 | | Tiberiu Seceleanu, Axel Jantsch, Hannu Tenhunen: On-Chip Distributed Architectures. SoCC 2006: 329-330 |
| 2005 | ||
| c42 | | Zhonghai Lu, Axel Jantsch, Ingo Sander: Feasibility analysis of messages for on-chip networks using wormhole routing. ASP-DAC 2005: 960-964 |
| c41 | | Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch: Modelling Environment for Heterogeneous Systems based on MoCs. FDL 2005: 291-303 |
| c40 | | Zhonghai Lu, Ingo Sander, Axel Jantsch: Refinement of Perfectly Synchronous Communication Model. FDL 2005: 453-465 |
| c39 | | Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch: System level verification of digital signal processing applications based on the polynomial abstraction technique. ICCAD 2005: 285-290 |
| c38 | | Axel Jantsch, Robert Lauter, Arseni Vitkovski: Power analysis of link level and end-to-end data protection in networks on chip. ISCAS (2) 2005: 1770-1773 |
| c37 | | Zhonghai Lu, Axel Jantsch: Traffic Configuration for Evaluating Networks on Chips. IWSOC 2005: 535-540 |
| e2 | | Petru Eles, Axel Jantsch, Reinaldo A. Bergamaschi (Eds.): Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005. ACM 2005, isbn 1-59593-161-9 |
| 2004 | ||
| j8 | | Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen: A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integration 38(1): 3-17 (2004) |
| j7 | | Axel Jantsch, Johnny Öberg, Hannu Tenhunen: Special issue on networks on chip. Journal of Systems Architecture 50(2-3): 61-63 (2004) |
| j6 | | Ingo Sander, Axel Jantsch: System modeling and transformational design refinement in ForSyDe [formal system design]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 17-32 (2004) |
| c36 | | Abhijit K. Deb, Axel Jantsch, Johnny Öberg: System design for DSP applications in transaction level modeling paradigm. DAC 2004: 466-471 |
| c35 | | Abhijit K. Deb, Axel Jantsch, Johnny Öberg: System Design for DSP Applications Using the MASIC Methodology. DATE 2004: 630-635 |
| c34 | | Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch: Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits. DATE 2004: 690-691 |
| c33 | | Mikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch: Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. DATE 2004: 890-895 |
| c32 | | Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch: The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. VLSI Design 2004: 693-696 |
| e1 | | Alex Orailoglu, Pai H. Chou, Petru Eles, Axel Jantsch (Eds.): Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004. ACM 2004, isbn 1-58113-937-3 |
| 2003 | ||
| c31 | | Tarvo Raudvere, Ingo Sander, Ashish Kumar Singh, Axel Jantsch: Verification of design decisions in ForSyDe. CODES+ISSS 2003: 176-181 |
| c30 | | Heiko Zimmer, Axel Jantsch: A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. CODES+ISSS 2003: 188-193 |
| c29 | | Ingo Sander, Axel Jantsch, Zhonghai Lu: Development and Application of Design Transformations in ForSyDe. DATE 2003: 10364-10369 |
| c28 | | Abhijit K. Deb, Johnny Öberg, Axel Jantsch: Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology. DATE 2003: 11100-11101 |
| c27 | | Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch: Load Distribution with the Proximity Congestion Awareness in a Network on Chip. DATE 2003: 11126-11127 |
| c26 | | |
| c25 | | Abhijit K. Deb, Johnny Öberg, Axel Jantsch: Simulation and Analysis of Embedded DSP Systems Using Petri Nets. IEEE International Workshop on Rapid System Prototyping 2003: 64-70 |
| c24 | | Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch: Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC 2003: 362- |
| c23 | | Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar: Extending Platform-Based Design to Network on Chip Systems. VLSI Design 2003: 401- |
| 2002 | ||
| c22 | | Per Bjuréus, Mikael Millberg, Axel Jantsch: FPGA resource and timing estimation from Matlab execution traces. CODES 2002: 31-36 |
| c21 | | Ingo Sander, Axel Jantsch: Transformation based communication and clock domain refinement for system design. DAC 2002: 281-286 |
| c20 | | Ingo Sander, Axel Jantsch, Zhonghai Lu: A Case Study of Hardware and Software Synthesis in ForSyDe. ISSS 2002: 86-91 |
| c19 | | Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani: A Network on Chip Architecture and Design Methodology. ISVLSI 2002: 117-124 |
| 2001 | ||
| j5 | | Mattias O'Nils, Axel Jantsch: Device Driver and DMA Controller Synthesis from HW /SW Communication Protocol Specifications. Design Autom. for Emb. Sys. 6(2): 177-205 (2001) |
| j4 | | Johnny Öberg, Mattias O'Nils, Axel Jantsch, Adam Postula, Ahmed Hemani: Grammar-based design of embedded systems. Journal of Systems Architecture 47(3-4): 225-240 (2001) |
| j3 | | Per Bjuréus, Axel Jantsch: Modeling of mixed control and dataflow systems in MASCOT. IEEE Trans. VLSI Syst. 9(5): 690-703 (2001) |
| c18 | | Axel Jantsch, Ingo Sander, Wenbiao Wu: The usage of stochastic processes in embedded system specifications. CODES 2001: 5-10 |
| c17 | | Per Bjuréus, Axel Jantsch: Performance analysis with confidence intervals for embedded software processes. ISSS 2001: 45-50 |
| c16 | | Abhijit K. Deb, Johnny Öberg, Axel Jantsch: Control and communication performance analysis of embedded DSP systems in the MASIC methodology. ISSS 2001: 274-273 |
| 2000 | ||
| j2 | | Axel Jantsch, Johann Notbauer, Thomas W. Albrecht: Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases. Design Autom. for Emb. Sys. 5(1): 83-113 (2000) |
| j1 | | Axel Jantsch, Shashi Kumar, Ahmed Hemani: A Metamodel for Studying Concepts in Electronic System Design. IEEE Design & Test of Computers 17(3): 78-85 (2000) |
| c15 | | Axel Jantsch, Ingo Sander: On the roles of functions and objects in system specification. CODES 2000: 8-12 |
| c14 | | Axel Jantsch, Per Bjuréus: Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors. DATE 2000: 154-160 |
| c13 | | Per Bjuréus, Axel Jantsch: MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow. DATE 2000: 161-168 |
| c12 | | Johan Ditmar, Kjell Torkelsson, Axel Jantsch: A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization. FPL 2000: 19-28 |
| 1999 | ||
| c11 | | Ingo Sander, Axel Jantsch: System synthesis utilizing a layered functional model. CODES 1999: 136-140 |
| c10 | | Axel Jantsch, Shashi Kumar, Ahmed Hemani: The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. DATE 1999: 256-262 |
| c9 | | Mattias O'Nils, Axel Jantsch: Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification. DATE 1999: 562-567 |
| c8 | | Mattias O'Nils, Axel Jantsch: Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols. VLSI Design 1999: 138-145 |
| c7 | | Ingo Sander, Axel Jantsch: Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons. VLSI Design 1999: 318-323 |
| 1998 | ||
| c6 | | Mattias O'Nils, Johnny Öberg, Axel Jantsch: Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces. EUROMICRO 1998: 10055-10058 |
| c5 | | Johnny Öberg, Axel Jantsch, Anshul Kumar: An Object-Oriented Concept for Intelligent Library Functions. VLSI Design 1998: 355-358 |
| 1996 | ||
| c4 | | Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen: A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. VLSI Design 1996: 23-28 |
| c3 | | Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani: A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. VLSI Design 1996: 133-139 |
| 1994 | ||
| c2 | | Axel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen: Hardware/software partitioning and minimizing memory interface traffic. EURO-DAC 1994: 226-231 |
| c1 | | Jouni Isoaho, Axel Jantsch, Hannu Tenhunen: DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques. FPL 1994: 318-320 |
Colors in the list of coauthors
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