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Abhijit Jas
2010 – today
- 2012
[j11]Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti: Functional Test-Sequence Grading at Register-Transfer Level. IEEE Trans. VLSI Syst. 20(10): 1890-1894 (2012)- 2011
- [j10]Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. IEEE Trans. Computers 60(9): 1260-1273 (2011)
- [j9]Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris: Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor. IEEE Trans. Computers 60(9): 1274-1287 (2011)
- [c21]Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: AVF Analysis Acceleration via Hierarchical Fault Pruning. European Test Symposium 2011: 87-92
- 2010
- [j8]Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 466-478 (2010)
- [c20]Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche: Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers 2010: 113-114
2000 – 2009
- 2009
- [j7]Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas: FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2) (2009)
- [c19]Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Impact analysis of performance faults in modern microprocessors. ICCD 2009: 91-96
- [c18]Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. VTS 2009: 9-14
- [c17]Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti: RT-Level Deviation-Based Grading of Functional Test Sequences. VTS 2009: 264-269
- 2008
- [j6]Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J. Electronic Testing 24(1-3): 259-269 (2008)
- [c16]Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC 2008: 486-491
- [c15]Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche: A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902
- [c14]Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti: Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. DFT 2008: 454-462
- [c13]Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche: Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. European Test Symposium 2008: 171-176
- [c12]Avijit Dutta, Abhijit Jas: Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. ISQED 2008: 68-73
- [c11]Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris: On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors. ITC 2008: 1-10
- 2007
- [c10]Abhijit Jas, Srinivas Patil: Analysis of Specified Bit Handling Capability of Combinational Expander Networks. DFT 2007: 252-260
- 2006
- [c9]Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: An Approach to Minimizing Functional Constraints. DFT 2006: 215-226
- 2004
- [j5]C. V. Krishna, Abhijit Jas, Nur A. Touba: Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Autom. Electr. Syst. 9(4): 500-516 (2004)
- [j4]Abhijit Jas, Bahram Pouya, Nur A. Touba: Test data compression technique for embedded cores using virtual scan chains. IEEE Trans. VLSI Syst. 12(7): 775-781 (2004)
- [j3]Abhijit Jas, C. V. Krishna, Nur A. Touba: Weighted pseudorandom hybrid BIST. IEEE Trans. VLSI Syst. 12(12): 1277-1283 (2004)
- 2003
- [j2]Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba: An efficient test vector compression scheme using selective Huffman coding. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 797-806 (2003)
- 2002
- [j1]Abhijit Jas, Nur A. Touba: Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. J. Electronic Testing 18(4-5): 503-514 (2002)
- 2001
- [c8]C. V. Krishna, Abhijit Jas, Nur A. Touba: Test vector encoding using partial LFSR reseeding. ITC 2001: 885-893
- [c7]Abhijit Jas, C. V. Krishna, Nur A. Touba: Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. VTS 2001: 2-8
- 2000
- [c6]Abhijit Jas, Bahram Pouya, Nur A. Touba: Virtual Scan Chains: A Means for Reducing Scan Length in Cores. VTS 2000: 73-78
1990 – 1999
- 1999
- [c5]Abhijit Jas, Kartik Mohanram, Nur A. Touba: An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium 1999: 275-
- [c4]Abhijit Jas, Nur A. Touba: Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. ICCD 1999: 418-
- [c3]W. Quddus, Abhijit Jas, Nur A. Touba: Configuration self-test in FPGA-based reconfigurable systems. ISCAS (1) 1999: 97-100
- [c2]Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba: Scan Vector Compression/Decompression Using Statistical Coding. VTS 1999: 114-120
- 1998
- [c1]Abhijit Jas, Nur A. Touba: Test vector decompression via cyclical scan chains and its application to testing core-based designs. ITC 1998: 458-464
Coauthor Index
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last updated on 2012-12-02 21:45 CET by the dblp team