Marcus Jeitler

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	2010
c4		Marcus Jeitler, Jakob Lechner, Andreas Steininger: Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. DDECS 2010: 233-236
c3		Marcus Jeitler, Jakob Lechner: Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. DSD 2010: 219-225
	2009
c2		Marcus Jeitler, Jakob Lechner: Towards Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection. MEMICS 2009
c1		Marcus Jeitler, Jakob Lechner: Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. ReConFig 2009: 65-70

Coauthor Index

1	Jakob Lechner	[c4] [c3] [c2] [c1]
2	Andreas Steininger	[c4]

Last update Thu May 23 01:52:46 2013 CET by the DBLP Team —

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