Jochen A. G. Jess

Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah: Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2376-2392 (2006)

Jochen A. G. Jess: Codeübersetzung unter Zeitvorgaben für eingebettete Signalprozessoren (Performance Controlled Compilation for Embedded Signal Processors). it - Information Technology 45(6): 327-335 (2003)

Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah: Statistical timing for parametric yield prediction of digital integrated circuits. DAC 2003: 932-937

Carlos A. Alba Pinto, Bart Mesman, Koen Van Eijk, Jochen A. G. Jess: Constraint satisfaction for storage files with Fifos or stacks during scheduling. DATE 2001: 824

Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess: Constraint Satisfaction for Relative Location Assignment and Scheduling. ICCAD 2001: 384-390

Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen: Phase coupled operation assignment for VLIW processors with distributed register files. ISSS 2001: 118-123

Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess: Static resource models of instruction sets. ISSS 2001: 159-164

Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess: Prophid: A Platform-Based Design Method. Design Autom. for Emb. Sys. 6(1): 5-37 (2000)

Jochen A. G. Jess: Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itself. IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1404-1427 (2000)

Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess: A code-motion pruning technique for global scheduling. ACM Trans. Design Autom. Electr. Syst. 5(1): 1-38 (2000)

Koen Van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess: Constraint analysis for code generation: basic techniques and applications in FACTS. ACM Trans. Design Autom. Electr. Syst. 5(4): 774-793 (2000)

Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess: Constraint analysis for DSP code generation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 44-57 (1999)

Luiz C. V. dos Santos, Jochen A. G. Jess: A Reordering Technique for Efficient Code Motion. DAC 1999: 296-299

Luiz C. V. dos Santos, Jochen A. G. Jess: Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation. DATE 1999: 609-

Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess: Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. DATE 1998: 125-131

Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess: A Constraint Driven Approach to Loop Pipelining and Register Binding. DATE 1998: 377-383

Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess: PROPHID: a data-driven multi-processor architecture for high-performance DSP. ED&TC 1997: 611

Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess: PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. ICCD 1997: 164-169

Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess: Constraint Analysis for DSP Code Generation. ISSS 1997: 33-40

Chennian Di, Jochen A. G. Jess: An efficient CMOS bridging fault simulator: with SPICE accuracy. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1071-1080 (1996)

Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess: Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1424-1434 (1996)

Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess: A Constructive Method for Exploiting Code Motion. ISSS 1996: 51-56

Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess: High-level synthesis scheduling and allocation using genetic algorithms. ASP-DAC 1995

Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess: Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. DAC 1995: 593-598

Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess: Routing for Manufacturability. DAC 1994: 402-406

Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess: On Design Rule Correct Maze Routing. EDAC-ETC-EUROASIC 1994: 407-411

Hua Xue, Chennian Di, Jochen A. G. Jess: Probability Analysis for CMOS Floating Gate Faults. EDAC-ETC-EUROASIC 1994: 443-448

Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess: Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. ICCAD 1994: 474-480

M. J. M. Heijiligers, H. A. Hilderink, Adwin H. Timmer, Jochen A. G. Jess: NEAT: An Object Oriented High-Level Synthesis Interface. ISCAS 1994: 233-236

Jochen A. G. Jess, Richard L. Rudell (Eds.): Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994, San Jose, California, USA, November 6-10, 1994. IEEE Computer Society 1994, isbn 0-89791-690-5

Ed P. Huijbregts, Jochen A. G. Jess: General gate array routing using a k-terminal net routing algorithm with failure prediction. IEEE Trans. VLSI Syst. 1(4): 473-481 (1993)

Hua Xue, Chennian Di, Jochen A. G. Jess: Fast Multi-Layer Critical Area Computation. DFT 1993: 117-124

Hua Xue, Chennian Di, Jochen A. G. Jess: A net-oriented method for realistic fault analysis. ICCAD 1993: 78-83

Adwin H. Timmer, Jochen A. G. Jess: Execution interval analysis under resource constraints. ICCAD 1993: 454-459

M. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess: Parameter Monitoring: Advantages and Pitfalls. ITC 1993: 115-124

Chennian Di, Jochen A. G. Jess: On Accurate Modeling and Efficient Simulation of CMOS Opens. ITC 1993: 875-882

Ed P. Huijbregts, Jochen A. G. Jess: A Multiple Terminal Net Routing Algorithm Using Failure Prediction. VLSI Design 1993: 84-89

Michael R. Lightner, Jochen A. G. Jess (Eds.): Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993. IEEE Computer Society 1993, isbn 0-8186-4490-7

Eric Bruls, F. Camerik, H. J. Kretschman, Jochen A. G. Jess: A Generic Method to Develop a Defect Monitoring System for IC Processes. ITC 1991: 218-227

Michel R. C. M. Berkelaar, Jochen A. G. Jess: Gate sizing in MOS digital circuits with linear programming. EURO-DAC 1990: 217-221

Gordon Adshead, Jochen A. G. Jess (Eds.): European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990. IEEE Computer Society 1990, isbn 0-8186-2024-2

José Pineda de Gyvez, Jochen A. G. Jess: On the design and implementation of a wafer yield editor. IEEE Trans. on CAD of Integrated Circuits and Systems 8(8): 920-925 (1989)

F. Camerik, P. A. J. Dirks, Jochen A. G. Jess: Qualification and Quantification of Process-Induced Product-Related Defects. ITC 1989: 643-652

Jochen A. G. Jess, H. G. M. Kees: A Data Structure for Parallel L/U Decomposition. IEEE Trans. Computers 31(3): 231-239 (1982)