Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Chris R. Jesshope
2010 – today
- 2013
[i1]Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, M. Irfan Uddin, Chris R. Jesshope: MGSim - Simulation tools for multi-core processor architectures. CoRR abs/1302.1390 (2013)- 2012
- [c42]Raphaël Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope: Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. DSD 2012: 501-508
- 2011
- [j22]M. Irfan Uddin, Michiel W. van Tol, Chris R. Jesshope: High Level Simulation of SVP Many-Core Systems. Parallel Processing Letters 21(4): 413-438 (2011)
- [c41]Qiang Yang, Chris R. Jesshope, Jian Fu: A Micro Threading Based Concurrency Model for Parallel Computing. IPDPS Workshops 2011: 1668-1674
- [c40]Michiel W. van Tol, Roy Bakker, Merijn Verstraaten, Clemens Grelck, Chris R. Jesshope: Efficient Memory Copy Operations on the 48-core Intel SCC Processor. MARC Symposium 2011: 13-18
- [c39]Merijn Verstraaten, Clemens Grelck, Michiel W. van Tol, Roy Bakker, Chris R. Jesshope: Mapping Distributed S-Net on the 48-core Intel SCC processor. MARC Symposium 2011: 41-46
- [c38]Clemens Grelck, Kevin Hammond, Heinz Hertlein, Philip K. F. Hölzenspies, Chris R. Jesshope, Raimund Kirner, Bernd Scheuermann, Alexander V. Shafarenko, Iraneus te Boekhorst, Volkmar Wieser: Engineering Concurrent Software Guided by Statistical Performance Analysis. PARCO 2011: 385-394
- 2010
- [j21]Thomas A. M. Bernard, Clemens Grelck, Chris R. Jesshope: On the Compilation of a Language for General Concurrent Target Architectures. Parallel Processing Letters 20(1): 51-69 (2010)
- [c37]Thomas A. M. Bernard, Clemens Grelck, Michael A. Hicks, Chris R. Jesshope, Raphaël Poss: Resource-Agnostic Programming for Many-Core Microgrids. Euro-Par Workshops 2010: 109-116
- [c36]Michiel W. van Tol, Chris R. Jesshope: An Operating System Strategy for General-purpose Parallel Computing on Many-core Architectures. High Performance Computing Workshop 2010: 157-181
- [c35]Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope: Towards scalable I/O on a many-core architecture. ICSAMOS 2010: 341-348
2000 – 2009
- 2009
- [j20]Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp: Implementation and evaluation of a microthread architecture. Journal of Systems Architecture - Embedded Systems Design 55(3): 149-161 (2009)
- [j19]Michiel W. van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra: An implementation of the SANE Virtual Processor using POSIX threads. Journal of Systems Architecture - Embedded Systems Design 55(3): 162-169 (2009)
- [j18]Chris R. Jesshope, Mike Lankamp, Li Zhang: The implementation of an SVP many-core processor and the evaluation of its memory architecture. SIGARCH Computer Architecture News 37(2): 38-45 (2009)
- [c34]Chris R. Jesshope, Mike Lankamp, Li Zhang: Evaluating CMPs and Their Memory Architecture. ARCS 2009: 246-257
- [c33]Martti Forsell, Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff: HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops 2009: 9-15
- [c32]Chris R. Jesshope, Michael A. Hicks, Mike Lankamp, Raphael 'kena' Poss, Li Zhang: Making multi-cores mainstream – from security to scalability. PARCO 2009: 16-31
- 2008
- [j17]Chris R. Jesshope: Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips. Parallel Processing Letters 18(2): 257-274 (2008)
- [c31]Thuy Duong Vu, Li Zhang, Chris R. Jesshope: The Verification of the On-Chip COMA Cache Coherence Protocol. AMAST 2008: 413-429
- [c30]Chris R. Jesshope: Building a Concurrency and Resource Allocation Model into a Processor's ISA. Euro-Par Workshops 2008: 129-130
- [c29]Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang: A general model of concurrency and its implementation as many-core dynamic RISC processors. ICSAMOS 2008: 1-9
- [c28]
- [c27]Chris R. Jesshope, Jean-Marc Philippe, Michiel W. van Tol: An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency. SAMOS 2008: 218-228
- 2007
- [j16]Nabil Hasasneh, Ian Bell, Chris R. Jesshope: Asynchronous arbiter for micro-threaded chip multiprocessors. Journal of Systems Architecture 53(5-6): 253-262 (2007)
- [c26]Nabil Hasasneh, Ian Bell, Chris R. Jesshope: High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids. AICCSA 2007: 301-308
- [c25]Li Zhang, Chris R. Jesshope: On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. Euro-Par Workshops 2007: 38-48
- [c24]Thuy Duong Vu, Chris R. Jesshope: Formalizing SANE Virtual Processor in Thread Algebra. ICFEM 2007: 345-365
- [c23]Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg: Strategies for Compiling µ TC to Novel Chip Multiprocessors. SAMOS 2007: 127-138
- [e3]Keqiu Li, Chris R. Jesshope, Hai Jin, Jean-Luc Gaudiot (Eds.): Network and Parallel Computing, IFIP International Conference, NPC 2007, Dalian, China, September 18-21, 2007, Proceedings. Lecture Notes in Computer Science 4672, Springer 2007, ISBN 978-3-540-74783-3
- 2006
- [j15]Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope: Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors. Comput. J. 49(2): 211-233 (2006)
- [j14]Chris R. Jesshope, Alexander V. Shafarenko: Special issue on Micro-grids - Guest Editor Introduction. International Journal of Parallel Programming 34(3): 189-192 (2006)
- [j13]Chris R. Jesshope, Alexander V. Shafarenko: Guest Editor's Introduction (Part 2). International Journal of Parallel Programming 34(4): 319-322 (2006)
- [j12]Ian Bell, Nabil Hasasneh, Chris R. Jesshope: Supporting Microthread Scheduling and Synchronisation in CMPs. International Journal of Parallel Programming 34(4): 343-381 (2006)
- [j11]Chris R. Jesshope: Microthreading a Model for Distributed Instruction-level Concurrency. Parallel Processing Letters 16(2): 209-228 (2006)
- [c22]Chris R. Jesshope: muTC - An Intermediate Language for Programming Chip Multiprocessors. Asia-Pacific Computer Systems Architecture Conference 2006: 147-160
- [c21]Nabil Hasasneh, Ian Bell, Chris R. Jesshope: Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors. ARCS 2006: 252-267
- [c20]Chris R. Jesshope: A Model for the Design and Programming of Multi-cores. High Performance Computing Workshop 2006: 37-55
- [e2]Chris R. Jesshope, Colin Egan (Eds.): Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings. Lecture Notes in Computer Science 4186, Springer 2006, ISBN 3-540-40056-7
- 2005
- [c19]Kostas Bousias, Chris R. Jesshope: The Challenges of Massive On-Chip Concurrency. Asia-Pacific Computer Systems Architecture Conference 2005: 157-170
- 2004
- [c18]Chris R. Jesshope: Microgrids - The exploitation of massive on-chip concurrency. High Performance Computing Workshop 2004: 203-223
- [c17]Lipeng Wen, Chris R. Jesshope: A General Learning Management System Based on Schema-driven Methodology. ICALT 2004: 0-
- [c16]
- 2003
- [c15]Chris R. Jesshope: Multi-threaded Microprocessors - Evolution or Revolution. Asia-Pacific Computer Systems Architecture Conference 2003: 21-45
- [c14]Lipeng Wen, Chris R. Jesshope: Web Services Technology and Learning Technology- A Web-Services Model for Constructing Decentralized Virtual Learning Environments. ICWS 2003: 507-514
- 2001
- [j10]Chris R. Jesshope: Cost-Effective Multimedia in On-line Teaching. Educational Technology & Society 4(3) (2001)
- [c13]Chris R. Jesshope: Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. ACSAC 2001: 80-88
- [c12]Ramón Beivide, Chris R. Jesshope, Antonio Robles, Cruz Izu: Topic 12: Routing and Communication in Interconnection Networks. Euro-Par 2001: 611-612
- [c11]Regina Gehne, Chris R. Jesshope, Zhenzi Zhang: Technology Integrated Learning Environment - A Web-based Distance Learning System. IMSA 2001: 1-6
- [c10]Hong Hong, Neena Albi, Kinshuk, Xiaoqin He, Ashok Patel, Chris R. Jesshope: Adaptivity in Web-based Educational System. WWW Posters 2001
- 2000
- [c9]
1990 – 1999
- 1999
- [j9]Chris R. Jesshope: Computers as Tutors: Solving the Crisis in Education. Educational Technology & Society 2(4) (1999)
- [c8]Chris R. Jesshope: Parallel Computer Architecture - What Is Its Future? Introduction. Euro-Par 1999: 695-697
- 1998
- [c7]Murray Pearson, Chris R. Jesshope: Multi-campus teaching using computer networks. ACSE 1998: 106-111
- 1997
- [j8]Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope: Optical Interconnectivity in a Scalable Data-Parallel System. J. Parallel Distrib. Comput. 41(1): 120-130 (1997)
- [c6]
- 1996
- [c5]Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, D. T. Nielson, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope: Optical Interconnection hardware for scalable systems. PDPTA 1996: 367-374
- 1994
- [c4]Cruz Izu, Ramón Beivide, Chris R. Jesshope: Mad-postman : A Look-ahead Message Propagation Method For Static Bidimensional Meshes. PDP 1994: 117-124
- [e1]Chris R. Jesshope, Vesselin Jossifov, Wolfgang Wilhelmi (Eds.): Parcella 1994, VI. International Workshop on Parallel Processing by Cellular Automata and Arrays, Potsdam, September 21-23, 1994. Proceedings. Mathematical Research 81, Akademie Verlag, Berlin 1994, ISBN 3-05-501602-5
- 1993
- [j7]Chris R. Jesshope, Cruz Izu: The MP1 Network Chip and its Application to Parallel Computers. Comput. J. 36(8): 763-777 (1993)
- [j6]Cruz Izu, Ramón Beivide, Chris R. Jesshope, Agustin Arruabarrena: Experimental evaluation of Mad Postman bidimensional routing networks. Microprocessing and Microprogramming 38(1-5): 33-41 (1993)
- [j5]
- 1991
- [c3]Vladimir Getov, Chris R. Jesshope: Simulation Facility of Distributed Memory System with "Mad Postman" Communication Network. EDMCC 1991: 224-233
1980 – 1989
- 1989
- [c2]Chris R. Jesshope, P. R. Miller, Jay T. Yantchev: High Performance Communications in Processor Networks. ISCA 1989: 150-157
- 1988
- [j4]Chris R. Jesshope: Transputers and switches as objects in OCCAM. Parallel Computing 8(1-3): 19-30 (1988)
- [c1]Chris R. Jesshope, Philip Miller, Jelio Yantchev: Programming with active data. Parcella 1988: 111-129
- 1985
- [j3]Chris R. Jesshope, M. J. Crawley, G. L. Lovegrove: An Intelligent Pascal Editor for a Graphical Oriented Workstation. Softw., Pract. Exper. 15(11): 1103-1119 (1985)
- 1980
- [j2]Chris R. Jesshope: The Implementation of Fast Radix 2 Transforms on Array Processors. IEEE Trans. Computers 29(1): 20-27 (1980)
- [j1]Chris R. Jesshope: Some Results Concerning Data Routing in Array Processors. IEEE Trans. Computers 29(7): 659-662 (1980)
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-06-04 22:16 CEST by the dblp team