Jie-Hong R. Jiang
List of publications from the DBLP Bibliography Server - FAQ
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 | 2012 | |
|---|---|---|
| j8 |      | Valeriy Balabanov, Jie-Hong R. Jiang: Unified QBF certification and its applications. Formal Methods in System Design 41(1): 45-65 (2012) |
| j7 | | Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang: Automatic Decoder Synthesis: Methods and Case Studies. IEEE Trans. on CAD of Integrated Circuits and Systems 31(9): 1319-1331 (2012) |
| j6 | | Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang: TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1723-1733 (2012) |
| c33 | | Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang: Clock rescheduling for timing engineering change orders. ASP-DAC 2012: 517-522 |
| c32 | | Cheng-Shen Han, Jie-Hong Roland Jiang: When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way. CAV 2012: 410-426 |
| c31 | | Yi-Ting Chung, Jie-Hong Roland Jiang: Functional timing analysis made fast and general. DAC 2012: 1055-1060 |
| c30 | | De-An Huang, Jie-Hong R. Jiang, Ruei-Yang Huang, Chi-Yun Cheng: Compiling program control flows into biochemical reactions. ICCAD 2012: 361-368 |
| c29 | | Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu: Improving design verifiability by early RTL coverability analysis. MEMOCODE 2012: 25-32 |
| c28 | | Valeriy Balabanov, Hui-Ju Katherine Chiang, Jie-Hong Roland Jiang: Henkin Quantifiers and Boolean Formulae. SAT 2012: 129-142 |
| 2011 | ||
| j5 | | Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang: Scalable don't-care-based logic optimization and resynthesis. TRETS 4(4): 34 (2011) |
| c27 | | Valeriy Balabanov, Jie-Hong R. Jiang: Resolution Proofs and Skolem Functions in QBF Evaluation and Applications. CAV 2011: 149-164 |
| c26 | | Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang: Towards completely automatic decoder synthesis. ICCAD 2011: 389-395 |
| c25 | | Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo: Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. ISQED 2011: 174-181 |
| 2010 | ||
| j4 | | Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang: To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers 59(4): 457-467 (2010) |
| c24 | | Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang: TRECO: dynamic technology remapping for timing engineering change orders. ASP-DAC 2010: 331-336 |
| c23 | | Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang: BooM: a decision procedure for boolean matching with abstraction and dynamic learning. DAC 2010: 499-504 |
| c22 | | Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang: Boolean matching of function vectors with strengthened learning. ICCAD 2010: 596-601 |
| c21 | | Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang: A robust functional ECO engine by SAT proof minimization and interpolation techniques. ICCAD 2010: 729-734 |
| 2009 | ||
| c20 | | |
| c19 | | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang: Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160 |
| c18 | | Jie-Hong Roland Jiang, Hsuan-Po Lin, Wei-Lun Hung: Interpolating functions from large Boolean relations. ICCAD 2009: 779-784 |
| 2008 | ||
| c17 | | Ruei-Rung Lee, Jie-Hong Roland Jiang, Wei-Lun Hung: Bi-decomposing large Boolean functions via interpolation and satisfiability solving. DAC 2008: 636-641 |
| c16 | | Hsuan-Po Lin, Jie-Hong Roland Jiang, Ruei-Rung Lee: To SAT or not to SAT: Ashenhurst decomposition in a large scale. ICCAD 2008: 32-37 |
| c15 | | Sz-Cheng Huang, Jie-Hong Roland Jiang: A dynamic accuracy-refinement approach to timing-driven technology mapping. ICCD 2008: 538-543 |
| 2007 | ||
| c14 | | Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko: Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD 2007: 227-233 |
| c13 | | Jie-Hong Roland Jiang, Wei-Lun Hung: Inductive equivalence checking under retiming and resynthesis. ICCAD 2007: 326-333 |
| c12 | | Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang: A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. PATMOS 2007: 148-159 |
| i1 | | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko: Efficient Solution of Language Equations Using Partitioned Representations. CoRR abs/0710.4743 (2007) |
| 2006 | ||
| j3 | | Jie-Hong Roland Jiang, Robert K. Brayton: Retiming and Resynthesis: A Complexity Perspective. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2674-2686 (2006) |
| 2005 | ||
| c11 | | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko: Efficient Solution of Language Equations Using Partitioned Representations. DATE 2005: 418-423 |
| c10 | | Jie-Hong Roland Jiang: On Some Transformation Invariants Under Retiming and Resynthesis. TACAS 2005: 413-428 |
| 2004 | ||
| c9 | | Jie-Hong Roland Jiang, Robert K. Brayton: Functional Dependency for Verification Reduction. CAV 2004: 268-280 |
| c8 | | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: On breakable cyclic definitions. ICCAD 2004: 411-418 |
| 2003 | ||
| j2 | | Jie-Hong Roland Jiang, Robert K. Brayton: On the verification of sequential equivalence. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 686-697 (2003) |
| c7 | | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: Reducing Multi-Valued Algebraic Operations to Binary. DATE 2003: 10752-10757 |
| 2002 | ||
| c6 | | Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa: Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002: 168- |
| c5 |  | Jie-Hong Roland Jiang, Robert K. Brayton: On the Verification of Sequential Equivalence. IWLS 2002: 307-314 |
| c4 | | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344 |
| 2001 | ||
| j1 | | Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. VLSI Syst. 9(2): 251-260 (2001) |
| 1999 | ||
| c3 | | Jie-Hong Roland Jiang, Iris Hui-Ru Jiang: Optimum loading dispersion for high-speed tree-type decision circuitry. ICCAD 1999: 520-525 |
| 1998 | ||
| c2 | | Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717 |
| 1997 | ||
| c1 | | Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei: BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. ASP-DAC 1997: 259-264 |
Colors in the list of coauthors
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