| 2012 | ||
|---|---|---|
| j5 | Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue: Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies. Journal of Circuits, Systems, and Computers 21(6) (2012) | |
| 2011 | ||
| j4 | Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue: A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect. IEICE Transactions 94-A(5): 1201-1209 (2011) | |
| 2010 | ||
| j3 | Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 250-260 (2010) | |
| 2009 | ||
| j2 | Zhangcai Huang, Minglu Jiang, Yasuaki Inoue: A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. IEICE Transactions 92-C(6): 806-814 (2009) | |
| j1 | Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue: Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model. IEICE Transactions 92-A(10): 2531-2539 (2009) | |
| 1 | Li Ding | |
| 2 | Shuai Fang | |
| 3 | Masanori Hashimoto | |
| 4 | Zhangcai Huang | |
| 5 | Yasuaki Inoue | |
| 6 | Atsushi Kurokawa | |
| 7 | Qiang Li | |
| 8 | Bin Lin | |
| 9 | Takashi Sato |
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