Ajay Joshi

Christopher Batten, Ajay Joshi, Vladimir Stojanovic, Krste Asanovic: Designing Chip-Level Nanophotonic Interconnection Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 137-153 (2012)

Zhen Wang, Mark G. Karpovsky, Ajay Joshi: Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes. IEEE Trans. VLSI Syst. 20(6): 1036-1048 (2012)

Zhen Wang, Mark G. Karpovsky, Ajay Joshi: Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories. IEEE Trans. VLSI Syst. 20(7): 1221-1234 (2012)

Mahmoud Zangeneh, Ajay Joshi: Performance and energy models for memristor-based 1T1R RRAM cell. ACM Great Lakes Symposium on VLSI 2012: 9-14

Ajay Joshi, Chao Chen, Zafar Takhirov, Bobak Nazer: A multi-layer approach to green computing: Designing energy-efficient digital circuits and manycore architectures. IGCC 2012: 1-3

Zafar Takhirov, Bobak Nazer, Ajay Joshi: Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit. ISQED 2012: 312-319

Ajay Joshi: Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems. VLSI Design 2012: 28

Jie Meng, Chao Chen, Ayse Kivilcim Coskun, Ajay Joshi: Run-time energy management of manycore systems through reconfigurable interconnects. ACM Great Lakes Symposium on VLSI 2011: 43-48

Zhen Wang, Mark G. Karpovsky, Ajay Joshi: Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasures. ACM Great Lakes Symposium on VLSI 2011: 359-362

Chao Chen, Jie Meng, Ayse Kivilcim Coskun, Ajay Joshi: Express Virtual Channels with Taps (EVC-T): A Flow Control Technique for Network-on-Chip (NoC) in Manycore Systems. Hot Interconnects 2011: 1-10

Zhen Wang, Mark G. Karpovsky, Ajay Joshi: Reliable MLC NAND flash memories based on nonlinear t-error-correcting codes. DSN 2010: 41-50

Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic: Re-architecting DRAM memory systems with monolithically integrated silicon photonics. ISCA 2010: 129-140

Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic: Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. IEEE Micro 29(4): 8-21 (2009)

Ajay Joshi, Byungsub Kim, Vladimir Stojanovic: Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects. Hot Interconnects 2009: 3-12

Zhen Wang, Mark G. Karpovsky, Berk Sunar, Ajay Joshi: Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes. ICICS 2009: 47-62

Scott Beamer, Krste Asanovic, Christopher Batten, Ajay Joshi, Vladimir Stojanovic: Designing multi-socket systems using silicon photonics. ICS 2009: 521-522

Ajay Joshi, Fred Chen, Vladimir Stojanovic: A Modeling and exploration framework for interconnect network design in the nanometer era. NOCS 2009: 91

Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, Vladimir Stojanovic: Silicon-photonic clos networks for global on-chip communication. NOCS 2009: 124-133

Nitesh V. Chawla, David A. Cieslak, Lawrence O. Hall, Ajay Joshi: Automatically countering imbalance and its empirical relationship to cost. Data Min. Knowl. Discov. 17(2): 225-252 (2008)

Yue Luo, Ajay Joshi, Aashish Phansalkar, Lizy Kurian John, Joydeep Ghosh: Analysing and improving clustering based sampling for microprocessor simulation. IJHPCN 5(4): 200-214 (2008)

Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John: Distilling the essence of proprietary workloads into miniature benchmarks. TACO 5(2) (2008)

Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic: Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. Hot Interconnects 2008: 21-30

Aashish Phansalkar, Ajay Joshi, Lizy K. John: Subsetting the SPEC CPU2006 benchmark suite. SIGARCH Computer Architecture News 35(1): 69-76 (2007)

Ajay Joshi, Yue Luo, Lizy K. John: Applying Statistical Sampling for Fast and Efficient Simulation of Commercial Workloads. IEEE Trans. Computers 56(11): 1520-1533 (2007)

Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis: Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. IEEE Trans. VLSI Syst. 15(9): 990-1002 (2007)

Aashish Phansalkar, Ajay Joshi, Lizy Kurian John: Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. ISCA 2007: 412-423

Ajay Joshi, Aashish Phansalkar, Lieven Eeckhout, Lizy Kurian John: Measuring Benchmark Similarity Using Inherent Program Characteristics. IEEE Trans. Computers 55(6): 769-782 (2006)

Joshua J. Yi, Resit Sendag, Lieven Eeckhout, Ajay Joshi, David J. Lilja, Lizy Kurian John: Evaluating Benchmark Subsetting Approaches. IISWC 2006: 93-104

Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John: Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks. IISWC 2006: 105-115

Ajay Joshi, Joshua J. Yi, Robert H. Bell Jr., Lieven Eeckhout, Lizy Kurian John, David J. Lilja: Evaluating the efficacy of statistical simulation for design space exploration. ISPASS 2006: 70-79

Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis: Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. VLSI Design 2006: 773-776

Ajay Joshi, Jeffrey A. Davis: Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI). IEEE Trans. VLSI Syst. 13(8): 899-910 (2005)

Ajay Joshi, Jeffrey A. Davis: Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. ACM Great Lakes Symposium on VLSI 2005: 446-451

Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, Lizy Kurian John: Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites. ISPASS 2005: 10-20

Yue Luo, Ajay Joshi, Aashish Phansalkar, Lizy Kurian John, Joydeep Ghosh: Analyzing and Improving Clustering Based Sampling for Microprocessor Simulation. SBAC-PAD 2005: 193-200

Ajay Joshi, Jeffrey A. Davis: Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing. SoCC 2005: 137-142

Ajay Joshi, Jeffrey A. Davis: A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). SLIP 2004: 64-68