Rajiv V. Joshi

Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha: Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 32(1): 47-58 (2013)

Rajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, D. Lea, D. Sciacca: Hardware-corroborated Variability-Aware SRAM Methodology. VLSI Design 2013: 344-349

Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif: Yield estimation via multi-cones. DAC 2012: 1107-1112

Peiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen: A thermal and process variation aware MTJ switching model and its applications in soft error analysis. ICCAD 2012: 720-727

Rouwaida Kanj, Rajiv V. Joshi: A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability. ISQED 2012: 672-678

Rajiv V. Joshi, Rouwaida Kanj, V. Ramadurai: A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. IEEE Trans. VLSI Syst. 19(5): 869-882 (2011)

Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif: The Impact of Statistical Leakage Models on Design Yield Estimation. VLSI Design 2011 (2011)

Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Helen Li: Universal statistical cure for predicting memory loss. ICCAD 2011: 236-239

Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif: Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD 2011: 353-360

Rajiv V. Joshi, Rouwaida Kanj, Anthony Pelella, Arthur Tuminaro, Yuen H. Chan: The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane. IEEE Design & Test of Computers 27(6): 36-45 (2010)

Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif: Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. ISLPED 2010: 337-342

Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv V. Joshi, Rouwaida Kanj: Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test. ISQED 2010: 315-319

Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj: FinFET SRAM Design. VLSI Design 2010: 440-445

Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif: An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. ICCAD 2009: 497-504

Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka: Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED 2009: 190-194

Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi: The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612

Rouwaida Kanj, Rajiv V. Joshi, Zhou Li, Jente B. Kuang, Hung C. Ngo, Ying Zhou, Weiping Shi, Sani R. Nassif: SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED 2008: 87-92

Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang: Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED 2008: 488-491

Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif: Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. ISQED 2008: 702-707

Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif: A Root-Finding Method for Assessing SRAM Stability. ISQED 2008: 804-809

Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)

Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang: A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED 2007: 8-13

Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif: Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40

Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang: A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design 2007: 665-672

Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif: Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. DAC 2006: 69-72

Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee: A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. DAC 2006: 977-982

Rajiv V. Joshi, Kaustav Banerjee, André DeHon: Tutorial 1: Emerging Technologies for VLSI Design. ISQED 2006: 4

Ruchir Puri, Tanay Karnik, Rajiv V. Joshi: Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design 2006: 5-7

Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, J. C. Law, Rajiv V. Joshi: A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. ICCD 2005: 574-584

Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi: Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4

Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415

Rajiv V. Joshi, S. S. Kang, N. Zamdmar, A. Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez: Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. VLSI Design 2005: 697-702

Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang: Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED 2004: 102-107

Rajiv V. Joshi, K. Kroell, Ching-Te Chuang: A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. VLSI Design 2004: 832-

Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy (Eds.): Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004. ACM 2004

E. N. Elnozahy, Rajiv V. Joshi: Preface. IBM Journal of Research and Development 47(5-6): 521-524 (2003)

Rosana Rodríguez, James H. Stathis, Barry P. Linder, Rajiv V. Joshi, Ching-Te Chuang: Influence and model of gate oxide breakdown on CMOS inverters. Microelectronics Reliability 43(9-11): 1439-1444 (2003)

Rajiv V. Joshi, Ching-Te Chuang, S. K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi: PD/SOI SRAM performance in presence of gate-to-body tunneling current. IEEE Trans. VLSI Syst. 11(6): 1106-1113 (2003)

Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri: Design and CAD Challenges in sub-90nm CMOS Technologies. ICCAD 2003: 129-137

Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown: New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. ISLPED 2003: 168-171

Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang: Strained-si devices and circuits for low-power applications. ISLPED 2003: 180-183

Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim: Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158

Rajiv V. Joshi, Kaushik Roy: Design of Deep Sub-Micron CMOS Circuits. VLSI Design 2003: 15-16

Rosana Rodríguez, James H. Stathis, Barry P. Linder, S. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, A. J. Bhavnagarwala, Salvatore Lombardo: Analysis of the effect of the gate oxide breakdown on SRAM stability. Microelectronics Reliability 42(9-11): 1445-1448 (2002)

Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang: SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42

W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi: Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266

Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty: IBM's Blue Logic Design Methodology-Circuits and Physical Design. VLSI Design 2001: 11-12

Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann: Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196-

Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang: "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206

Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang: A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49

Rajiv V. Joshi, Wei Hwang: Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design 1999: 526-531

Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin G. Stawiasz: Designing a Testable System on a Chip. VTS 1998: 2-7

W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi: Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285

Wei Hwang, Rajiv V. Joshi, Walter H. Henkels: A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD 1997: 712-717