Jing-Yang Jou

Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou: Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. ASP-DAC 2013: 338-343

Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou: Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Transactions 95-A(2): 559-566 (2012)

Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou: Thread affinity mapping for irregular data access on shared Cache GPGPU. ASP-DAC 2012: 659-664

Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC 2011: 497-502

Meng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou: Mixed non-rectangular block packing for non-Manhattan layout architectures. ISQED 2011: 257-262

Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen: Design-for-debug layout adjustment for FIB probing and circuit editing. ITC 2011: 1-9

Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou: FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26(5): 1601-1617 (2010)

Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou: Unleash the parallelism of 3DIC partitioning on GPGPU. SoCC 2010: 127-132

Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou: Expandable MDC-based FFT architecture and its generator for high-performance applications. SoCC 2010: 188-192

Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 272-284 (2009)

Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou: Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. ACM Trans. Design Autom. Electr. Syst. 15(1) (2009)

Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. VLSI Syst. 17(5): 723-727 (2009)

Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu: Multiple-Fault Diagnosis Using Faulty-Region Identification. VTS 2009: 123-128

Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou: Verification of Pin-Accurate Port Connections. IEEE Design & Test of Computers 25(5): 478-486 (2008)

Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou: A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23(1): 71-90 (2007)

Cheng-Yeh Wang, Chih-Bin Kuo, Jing-Yang Jou: Hybrid Wordlength Optimization Methods of Pipelined FFT Processors. IEEE Trans. Computers 56(8): 1105-1118 (2007)

Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1509-1521 (2007)

Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou: A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC 2007: 165-170

Chia-Chih Yen, Jing-Yang Jou: An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging. IEEE Trans. Computers 55(11): 1356-1366 (2006)

Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou: RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2258-2264 (2006)

Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou: Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006)

Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC 2006: 448-453

Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou: A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC 2006: 600-605

Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou: Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. SoCC 2006: 137-140

Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou: An efficient heterogeneous tree multiplexer synthesis technique. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1622-1629 (2005)

Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou: Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. ASP-DAC 2005: 39-44

Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC 2005: 323-326

Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. HLDVT 2005: 87-93

Chia-Chih Yen, Jing-Yang Jou: An optimum algorithm for compacting error traces for efficient functional debugging. HLDVT 2005: 177-183

Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) 2005: 4134-4137

Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen: A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Design & Test of Computers 21(2): 111-120 (2004)

Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao: Simultaneous floor plan and buffer-block optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004)

Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273

Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou: Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. ASP-DAC 2004: 280-283

Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou: On compliance test of on-chip bus for SOC. ASP-DAC 2004: 328-333

Chia-Chih Yen, Jing-Yang Jou: Enhancing sequential depth computation with a branch-and-bound algorithm. HLDVT 2004: 3-8

Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou: Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. ICCD 2004: 417-419

Yi-Wei Lin, Jing-Yang Jou: An efficient approach for hierarchical submodule extraction. ISCAS (5) 2004: 237-240

Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang: An efficient logic extraction algorithm using partitioning and circuit encoding. ISCAS (5) 2004: 249-252

Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) 2004: 945-948

Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang: Verification on Port Connections. ITC 2004: 830-836

Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: A Design-for-Verification Technique for Functional Pattern Reduction. IEEE Design & Test of Computers 20(2): 48-55 (2003)

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 104-114 (2003)

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An automatic interconnection rectification technique for SoC design integration. ASP-DAC 2003: 108-111

Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao: Simultaneous floorplanning and buffer block planning. ASP-DAC 2003: 431-434

Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou: An efficient IP-level power model for complex digital circuits. ASP-DAC 2003: 610-613

Che-Hua Shih, Jing-Yang Jou: An efficient approach for error diagnosis in HDL design. ISCAS (4) 2003: 732-735

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: SoC design integration by using automatic interconnection rectification. ISCAS (4) 2003: 744-747

Heng-Liang Huang, Jing-Yang Jou: Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation. Journal of Circuits, Systems, and Computers 11(4): 333-350 (2002)

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 466-479 (2002)

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1225-1232 (2002)

Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium 2002: 362-367

Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou: A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS 2002: 149-154

Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou: Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 172-176 (2001)

Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. VLSI Syst. 9(2): 251-260 (2001)

Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: An efficient design-for-verification technique for HDLs. ASP-DAC 2001: 103-108

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. Asian Test Symposium 2001: 431-436

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. HLDVT 2001: 145-150

Hen-Ming Lin, Jing-Yang Jou: On tri-state buffer inference in HDL synthesis. ISCAS (5) 2001: 45-48

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An AVPG for SOC design verification with port order fault model. ISCAS (5) 2001: 259-262

Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen: Grouped input power sensitive transition an input sequence compaction technique for power estimation. ISCAS (5) 2001: 471-474

Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou: Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED 2001: 372-377

Chien-Nan Jimmy Liu, Jing-Yang Jou: An Automatic Controller Extractor for HDL Descriptions at the RTL. IEEE Design & Test of Computers 17(3): 72-77 (2000)

Hen-Ming Lin, Jing-Yang Jou: On computing the minimum feedback vertex set of a directed graph bycontraction operations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 295-307 (2000)

Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou: Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 999-1010 (2000)

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 8(4): 392-400 (2000)

Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A new method for constructing IP level power model based on power sensitivity. ASP-DAC 2000: 135-140

Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17-

Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou: Optimal reliable crosstalk-driven interconnect optimization. ISPD 2000: 128-133

Jyh-Mou Tseng, Jing-Yang Jou: Two-level logic minimization for low power. ACM Trans. Design Autom. Electr. Syst. 4(1): 52-69 (1999)

Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A structure-oriented power modeling technique for macrocells. IEEE Trans. VLSI Syst. 7(3): 380-391 (1999)

Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang: Hierarchical Floorplan Design on the Internet. ASP-DAC 1999: 189-192

Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang: Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC 1999: 90-95

Chien-Nan Jimmy Liu, Jing-Yang Jou: An Efficient Functional Coverage Test for HDL Descriptions at RTL. ICCD 1999: 325-327

Hen-Ming Lin, Jing-Yang Jou: Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. ICCD 1999: 364-

Shing-Wu Tung, Jing-Yang Jou: A Logical Fault Model for Library Coherence Checking. J. Inf. Sci. Eng. 14(3): 567-586 (1998)

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang: On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. VLSI Syst. 6(4): 634-642 (1998)

Shing-Wu Tung, Jing-Yang Jou: Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. Asian Test Symposium 1998: 402-407

Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717

Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo: Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1015-1024 (1997)

Jyh-Mou Tseng, Jing-Yang Jou: A power driven two-level logic optimizer. ASP-DAC 1997: 113-116

Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei: BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. ASP-DAC 1997: 259-264

Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A power modeling and characterization method for macrocells using structure information. ICCAD 1997: 502-506

Jing-Yang Jou, Ming-Chang Nien: Power Driven Partial Scan. ICCD 1997: 642-647

Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao: Easily Testable Data Path Allocation Using Input/Output Registers. Asian Test Symposium 1996: 142-

Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo: An Efficient PRPG Strategy By Utilizing Essential Faults. Asian Test Symposium 1996: 199-204

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17

Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A power modeling and characterization method for the CMOS standard cell library. ICCAD 1996: 400-404

Jing-Yang Jou, Kwang-Ting (Tim) Cheng: Timing-Driven Partial Scan. IEEE Design & Test of Computers 12(4): 52-59 (1995)

Jing-Yang Jou: An effective BIST design for PLA. Asian Test Symposium 1995: 286-292

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD 1995: 359-363

Kwang-Ting Cheng, Jing-Yang Jou: A functional fault model for sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1065-1073 (1992)

Jing-Yang Jou, Kwang-Ting Cheng: Timing-Driven Partial Scan. ICCAD 1991: 404-407

Kwang-Ting Cheng, Jing-Yang Jou: A Single-State-Transition Fault Model for Sequential Machines. ICCAD 1990: 226-229

Kwang-Ting Cheng, Jing-Yang Jou: Functional test generation for finite state machines. ITC 1990: 162-168

Jing-Yang Jou, Jacob A. Abraham: Fault-Tolerant FFT Networks. IEEE Trans. Computers 37(5): 548-561 (1988)

Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou: BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. DAC 1988: 409-414

Jing-Yang Jou, Jacob A. Abraham: Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. ICPP (1) 1988: 359-362