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 | 2012 | |
|---|---|---|
| c3 |      | Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Bit error rate estimation in SRAM considering temperature fluctuation. ISQED 2012: 516-519 |
| 2011 | ||
| j1 | | Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Transactions 94-A(12): 2693-2700 (2011) |
| c2 | | Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC 2011: 1-4 |
| c1 | | Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto: Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED 2011: 322-325 |
| 1 | Shintaro Izumi | |
| 2 | Hiroshi Kawaguchi | |
| 3 | Yohei Nakata | |
| 4 | Shunsuke Okumura | |
| 5 | Koji Yanagida | |
| 6 | Masahiro Yoshikawa | |
| 7 | Masahiko Yoshimoto | |
| 8 | Shusuke Yoshimoto |
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