Andrew B. Kahng

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath: Optimization of overdrive signoff. ASP-DAC 2013: 344-349

Andrew B. Kahng, Siddhartha Nath, Tajana Rosing: On potential design impacts of electromigration awareness. ASP-DAC 2013: 527-532

Andrew B. Kahng, Seokhyeong Kang, Bongil Park: Active-mode leakage reduction with data-retained power gating. DATE 2013: 1209-1214

Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng: Impact of adaptive voltage scaling on aging-aware signoff. DATE 2013: 1683-1688

Andrew B. Kahng, Bill Lin, Siddhartha Nath: Enhanced metamodeling techniques for high-dimensional IC design estimation problems. DATE 2013: 1861-1866

Andrew B. Kahng: Predicting the future of information technology and society [The Road Ahead]. IEEE Design & Test of Computers 29(6): 101-102 (2012)

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 404-417 (2012)

Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi: ORION 2.0: A Power-Area Simulator for Interconnection Networks. IEEE Trans. VLSI Syst. 20(1): 191-196 (2012)

Andrew B. Kahng, Bill Lin, Siddhartha Nath: Explicit modeling of control and data for improved NoC router estimation. DAC 2012: 392-397

Andrew B. Kahng, Seokhyeong Kang: Accuracy-configurable adder for approximate arithmetic designs. DAC 2012: 820-825

Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong: MAPG: Memory access power gating. DATE 2012: 1054-1059

Tuck-Boon Chan, Andrew B. Kahng: Tunable sensors for process-aware voltage scaling. ICCAD 2012: 7-14

Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov: Sensitivity-guided metaheuristics for accurate discrete gate sizing. ICCAD 2012: 233-239

Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas: CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD 2012: 294-301

Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong: TAP: token-based adaptive power gating. ISLPED 2012: 203-208

Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng: Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. ISPD 2012: 105-112

Andrew B. Kahng, Seokhyeong Kang: Construction of realistic gate sizing benchmarks with known optimal solutions. ISPD 2012: 153-160

Tuck-Boon Chan, Andrew B. Kahng: Improved path clustering for adaptive path-delay testing. ISQED 2012: 13-20

Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai: DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators. ISQED 2012: 633-640

Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu: VLSI Physical Design - From Graph Partitioning to Timing Closure. Springer 2011, isbn 978-90-481-9590-9, pp. I-XI, 1-310

Andrew B. Kahng: Design for manufacturability: Then and now. IEEE Design & Test of Computers 28(1): 76-77 (2011)

Andrew B. Kahng: Roads not taken. IEEE Design & Test of Computers 28(2): 74-75 (2011)

Andrew B. Kahng: The Future of Signoff. IEEE Design & Test of Computers 28(3): 86-89 (2011)

Andrew B. Kahng: Roadmapping Power. IEEE Design & Test of Computers 28(5): 104-106 (2011)

Andrew B. Kahng: Product Futures. IEEE Design & Test of Computers 28(6): 88-89 (2011)

Andrew B. Kahng, Vijayalakshmi Srinivasan: Big Chips. IEEE Micro 31(4): 3-5 (2011)

Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong: More realistic power grid verification based on hierarchical current and power constraints. ISPD 2011: 159-166

Sung Kyu Han, Kwangok Jeong, Andrew B. Kahng, Jingwei Lu: Stability and scalability in global routing. SLIP 2011: 1-6

Kwangok Jeong, Andrew B. Kahng: Toward PDN resource estimation: A law of general power density. SLIP 2011: 1-6

Andrew B. Kahng, Vaishnav Srinivas: Mobile system considerations for SDRAM interface trends. SLIP 2011: 1-8

Andrew B. Kahng: Scaling: More than Moore's law. IEEE Design & Test of Computers 27(3): 86-87 (2010)

Andrew B. Kahng: When is 3D 2B? IEEE Design & Test of Computers 27(4): 70-71 (2010)

Kwangok Jeong, Andrew B. Kahng, B. Lin, Kambiz Samadi: Accurate Machine-Learning-Based On-Chip Router Modeling. Embedded Systems Letters 2(3): 62-66 (2010)

Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao: Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. on CAD of Integrated Circuits and Systems 29(6): 939-952 (2010)

Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao: Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1070-1082 (2010)

Mohit Gupta, Kwangok Jeong, Andrew B. Kahng: Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography. IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1229-1242 (2010)

Luca P. Carloni, Andrew B. Kahng, Sudhakar Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma: Accurate Predictive Interconnect Modeling for System-Level Design. IEEE Trans. VLSI Syst. 18(4): 679-684 (2010)

Andrew B. Kahng, Bill Lin, Kambiz Samadi: Improved on-chip router analytical power and area modeling. ASP-DAC 2010: 241-246

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC 2010: 825-831

Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam: Trace-driven optimization of networks-on-chip configurations. DAC 2010: 437-442

Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma: Eyecharts: constructive benchmarking of gate sizing heuristics. DAC 2010: 597-602

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC 2010: 825-830

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA 2010: 1-11

Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam: Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations. ICCAD 2010: 256-263

Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang: Toward effective utilization of timing exceptions in design optimization. ISQED 2010: 54-61

Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu: Assessing chip-level impact of double patterning lithography. ISQED 2010: 122-130

Kwangok Jeong, Andrew B. Kahng: Methodology from chaos in IC implementation. ISQED 2010: 885-892

Chung-Kuan Cheng, Andrew B. Kahng, Kambiz Samadi, Amirali Shayan Arani: Worst-case performance prediction under supply voltage and temperature variation. SLIP 2010: 91-96

Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang: Lens aberration aware placement for timing yield. ACM Trans. Design Autom. Electr. Syst. 14(1) (2009)

Kwangok Jeong, Andrew B. Kahng: Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography. ASP-DAC 2009: 486-491

Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi: ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. DATE 2009: 423-428

Ayse Kivilcim Coskun, Andrew B. Kahng, Tajana Simunic Rosing: Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. DSD 2009: 183-190

Mohit Gupta, Kwangok Jeong, Andrew B. Kahng: Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. ICCAD 2009: 607-614

Kwangok Jeong, Andrew B. Kahng, Hailong Yao: Revisiting the linear programming framework for leakage power vs. performance optimization. ISQED 2009: 127-134

Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu: Is overlay error more important than interconnect variations in double patterning? SLIP 2009: 3-10

Andrew B. Kahng, Kambiz Samadi: CMP Fill Synthesis: A Survey of Recent Studies. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 3-19 (2008)

Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma: Defocus-Aware Leakage Estimation and Control. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 230-240 (2008)

Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu: Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1241-1252 (2008)

Andrew B. Kahng, Chul-Hong Park, Xu Xu: Fast Dual-Graph-Based Hotspot Filtering. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1635-1642 (2008)

Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma: Interconnect modeling for improved system-level design optimization. ASP-DAC 2008: 258-264

Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Investigation of diffusion rounding for post-lithography analysis. ASP-DAC 2008: 480-485

Puneet Gupta, Andrew B. Kahng: Bounded-lifetime integrated circuits. DAC 2008: 347-348

Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao: Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC 2008: 516-521

Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh: DFM in practice: hit or hype? DAC 2008: 898-899

Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao: Layout decomposition for double patterning lithography. ICCAD 2008: 465-472

Andrew B. Kahng: How to get real mad. ISPD 2008: 69

Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi: Quantified Impacts of Guardband Reduction on Design Process Outcomes. ISQED 2008: 790-797

Andrew B. Kahng, Ira Chayut, John M. Cohn, Toshihiro Hattori, Jeong-Taek Kong, Pierre G. Paulin, Rich Tobias: Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs. IEEE Design & Test of Computers 24(1): 83-93 (2007)

Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky: Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 115-126 (2007)

Andrew B. Kahng, Ion I. Mandoiu, Xu Xu, Alexander Zelikovsky: Enhanced Design Flow and Optimizations for Multiproject Wafers. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 301-311 (2007)

Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong: Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L_eff Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 845-857 (2007)

Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1614-1624 (2007)

Andrew B. Kahng, Bao Liu, Xu Xu: Statistical Timing Analysis in the Presence of Signal-Integrity Effects. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1873-1877 (2007)

Puneet Gupta, Andrew B. Kahng, Chul-Hong Park: Detailed Placement for Enhanced Control of Resist and Etch CDs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2144-2157 (2007)

Andrew B. Kahng, Bao Liu, Qinke Wang: Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. IEEE Trans. VLSI Syst. 15(8): 904-912 (2007)

Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman: A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC 2007: 24-31

Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Line-End Shortening is Not Always a Failure. DAC 2007: 270-271

Andrew B. Kahng: Design challenges at 65nm and beyond. DATE 2007: 1466-1467

Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu: Exploiting STI stress for performance. ICCAD 2007: 83-90

Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu: Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. ICCD 2007: 71-77

Andrew B. Kahng, Swamy Muddu, Puneet Sharma: Detailed placement for leakage reduction using systematic through-pitch variation. ISLPED 2007: 110-115

Andrew B. Kahng, Rasit Onur Topaloglu: A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances. ISQED 2007: 467-474

Andrew B. Kahng, Sherief Reda, Puneet Sharma: On-Line Adjustable Buffering for Runtime Power Reduction. ISQED 2007: 550-555

Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky: Bright-Field AAPSM Conflict Detection and Correction. CoRR abs/0710.4661 (2007)

Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky: Computer-Aided Optimization of DNA Array Design and Manufacturing. IEEE Trans. on CAD of Integrated Circuits and Systems 25(2): 305-320 (2006)

Andrew B. Kahng, Sherief Reda: New and improved BIST diagnosis methods from combinatorial Group testing theory. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 533-543 (2006)

Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng: A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 678-691 (2006)

Andrew B. Kahng, Sherief Reda: Wirelength minimization for min-cut placements via placement feedback. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1301-1312 (2006)

Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Gate-length biasing for runtime-leakage control. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1475-1485 (2006)

Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu: Wafer Topography-Aware Optical Proximity Correction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2747-2756 (2006)

Andrew B. Kahng, Sherief Reda: Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2806-2819 (2006)

Andrew B. Kahng: CAD challenges for leading-edge multimedia designs. DAC 2006: 372

Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang: Timing-driven Steiner trees are (practically) free. DAC 2006: 389-392

Saumil Shah, Puneet Gupta, Andrew B. Kahng: Standard cell library optimization for leakage reduction. DAC 2006: 983-986

Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang: Lens aberration aware timing-driven placement. DATE 2006: 890-895

Andrew B. Kahng, Bao Liu, Xu Xu: Statistical gate delay calculation with crosstalk alignment consideration. ACM Great Lakes Symposium on VLSI 2006: 223-228

Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky: Fill for shallow trench isolation CMP. ICCAD 2006: 661-668

Rasit Onur Topaloglu, Andrew B. Kahng: Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. ICCD 2006

Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: Efficient decoupling capacitor planning via convex programming methods. ISPD 2006: 102-107

Andrew B. Kahng, Qinke Wang: A faster implementation of APlace. ISPD 2006: 218-220

Andrew B. Kahng, Bao Liu, Xu Xu: Constructing Current-Based Gate Models Based on Existing Timing Library. ISQED 2006: 37-42

Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. ISQED 2006: 638-643

Andrew B. Kahng, Kambiz Samadi, Puneet Sharma: Study of Floating Fill Impact on Interconnect Capacitance. ISQED 2006: 691-696

Andrew B. Kahng, Swamy Muddu, Puneet Sharma: Impact of Gate-Length Biasing on Threshold-Voltage Selection. ISQED 2006: 747-754

Andrew B. Kahng, Sherief Reda: A tale of two nets: studies of wirelength progression in physical design. SLIP 2006: 17-24

Andrew B. Kahng, Rasit Onur Topaloglu: Generation of design guarantees for interconnect matching. SLIP 2006: 29-34

Andrew B. Kahng, Bao Liu, Xu Xu: Statistical crosstalk aggressor alignment aware interconnect delay calculation. SLIP 2006: 91-97

Puneet Gupta, Andrew B. Kahng: Efficient Design and Analysis of Robust Power Distribution Meshes. VLSI Design 2006: 337-342

Andrew B. Kahng, Grant Martin: DAC Highlights. IEEE Design & Test of Computers 22(3): 197-199 (2005)

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao: The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 588-599 (2005)

Andrew B. Kahng, Qinke Wang: Implementation and extensibility of an analytic placer. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 734-747 (2005)

Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma: Layout-aware scan chain synthesis for improved path delay fault coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1104-1114 (2005)

Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng: Compressible area fill synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1169-1187 (2005)

Puneet Gupta, Andrew B. Kahng, Stefanus Mantik: Routing-aware scan chain ordering. ACM Trans. Design Autom. Electr. Syst. 10(3): 546-560 (2005)

Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen: Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC 2005

Puneet Gupta, Andrew B. Kahng, Chul-Hong Park: Detailed placement for improved depth of focus and CD control. ASP-DAC 2005: 343-348

Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. DAC 2005: 365-368

Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang: Power-aware placement. DAC 2005: 795-800

Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky: Bright-Field AAPSM Conflict Detection and Correction. DATE 2005: 908-913

Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu: Fast and efficient phase conflict detection and correction in standard-cell layouts. ICCAD 2005: 149-156

Andrew B. Kahng, Sherief Reda: Intrinsic shortest path length: a new, accurate a priori wirelength estimator. ICCAD 2005: 173-180

Andrew B. Kahng, Sherief Reda, Qinke Wang: Architecture and details of a high quality, large-scale analytical placer. ICCAD 2005: 891-898

Andrew B. Kahng, Bao Liu, Qinke Wang: Supply Voltage Degradation Aware Analytical Placement. ICCD 2005: 437-443

Andrew B. Kahng, Swamy Muddu, Puneet Sharma: Defocus-aware leakage estimation and control. ISLPED 2005: 263-268

Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong: Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ISPD 2005: 78-85

Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia: A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207

Andrew B. Kahng, Sherief Reda: Evaluation of placer suboptimality via zero-change netlist transformations. ISPD 2005: 208-215

Andrew B. Kahng, Sherief Reda, Qinke Wang: APlace: a general analytic placement framework. ISPD 2005: 233-235

Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Performance Driven OPC for Mask Cost Reduction. ISQED 2005: 270-275

Puneet Gupta, Andrew B. Kahng, Puneet Sharma: A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. ISQED 2005: 421-426

William H. Joyner Jr., Grant Martin, Andrew B. Kahng (Eds.): Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005. ACM 2005, isbn 1-59593-058-2

Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky: Multicommodity Flow Algorithms for Buffered Global Routing. CoRR abs/cs/0508045 (2005)

Don Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian: 2003 Technology Roadmap for Semiconductors. IEEE Computer 37(1): 47-56 (2004)

Dwight D. Hill, Andrew B. Kahng: Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice. IEEE Design & Test of Computers 21(1): 9-12 (2004)

Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky: Scalable Heuristics for Design of DNA Probe Arrays. Journal of Computational Biology 11(2/3): 429-447 (2004)

Andrew B. Kahng, Sherief Reda: Match twice and stitch: a new TSP tour construction heuristic. Oper. Res. Lett. 32(6): 499-509 (2004)

Andrew B. Kahng, Bao Liu, Ion I. Mandoiu: Nontree routing for reliability and yield improvement [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 148-156 (2004)

Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong: Effective iterative techniques for fingerprinting design IP. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 208-215 (2004)

Andrew B. Kahng, Xu Xu: Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 464-471 (2004)

Andrew B. Kahng, Sherief Reda: Combinatorial group testing methods for the BIST diagnosis problem. ASP-DAC 2004: 113-116

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang: Optimal planning for mesh-based power distribution. ASP-DAC 2004: 444-449

Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Toward a methodology for manufacturability-driven design rule exploration. DAC 2004: 311-316

Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Selective gate-length biasing for cost-effective runtime leakage control. DAC 2004: 327-330

Andrew B. Kahng, Sherief Reda: Placement feedback: a concept and method for better min-cut placements. DAC 2004: 357-362

Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier: Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. DAC 2004: 363-368

Andrew B. Kahng, Igor L. Markov, Sherief Reda: Boosting: Min-Cut Placement with Improved Signal Delay. DATE 2004: 1098-1103

Andrew B. Kahng, Igor L. Markov, Sherief Reda: On legalization of row-based placements. ACM Great Lakes Symposium on VLSI 2004: 214-219

Andrew B. Kahng, Qinke Wang: An analytic placer for mixed-size placement and timing-driven placement. ICCAD 2004: 565-572

Andrew B. Kahng, Qinke Wang: Implementation and extensibility of an analytic placer. ISPD 2004: 18-25

Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu, Alexander Zelikovsky: Multi-project reticle floorplanning and wafer dicing. ISPD 2004: 70-77

Andrew B. Kahng: Manufacturability . ISQED 2004: 8

Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Investigation of performance metrics for interconnect stack architectures. SLIP 2004: 23-29

Puneet Gupta, Andrew B. Kahng: Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. VLSI Design 2004: 431-436

Sharad Malik, Limor Fix, Andrew B. Kahng (Eds.): Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004. ACM 2004, isbn 1-58113-828-8

Andrew B. Kahng: Error Tolerance. IEEE Design & Test of Computers 20(1): 86-87 (2003)

Andrew B. Kahng: Bringing down NRE. IEEE Design & Test of Computers 20(3): 110-111 (2003)

Andrew B. Kahng: How much variability can designers tolerate? IEEE Design & Test of Computers 20(6): 96-97 (2003)

Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky: Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 241-253 (2003)

Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky: On the skew-bounded minimum-buffer routing tree problem. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 937-945 (2003)

Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hierarchical whitespace allocation in top-down placement. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1550-1556 (2003)

Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. VLSI Syst. 11(1): 3-14 (2003)

Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky: Highly scalable algorithms for rectilinear and octilinear Steiner trees. ASP-DAC 2003: 827-833

Puneet Gupta, Andrew B. Kahng, Stefanus Mantik: Routing-aware scan chain ordering. ASP-DAC 2003: 857-862

Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. DAC 2003: 16-21

Yu Chen, Puneet Gupta, Andrew B. Kahng: Performance-impact limited area fill synthesis. DAC 2003: 22-27

Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf: Nanometer design: place your bets. DAC 2003: 546-547

Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu: An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799

Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu: A Novel Metric for Interconnect Architecture Performance. DATE 2003: 10448-10455

Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng: Area Fill Generation With Inherent Data Volume Reduction. DATE 2003: 10868-10875

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao: The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD 2003: 13-20

Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky: Evaluation of Placement Techniques for DNA Probe Array Layout. ICCAD 2003: 262-269

Puneet Gupta, Andrew B. Kahng: Manufacturing-Aware Physical Design. ICCAD 2003: 681-688

Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma: Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. ICCAD 2003: 754-759

Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky: Design Flow Enhancements for DNA Arrays. ICCD 2003: 116-

Andrew B. Kahng, Xu Xu: Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning. ISPD 2003: 81-86

Andrew B. Kahng: Research directions for coevolution of rules and routers. ISPD 2003: 122-125

Andrew B. Kahng, Igor L. Markov: Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint. ISQED 2003: 208-213

Puneet Gupta, Andrew B. Kahng: Quantifying Error in Dynamic Power Estimation of CMOS Circuits. ISQED 2003: 273-278

Puneet Gupta, Andrew B. Kahng, Stefanus Mantik: A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. ISQED 2003: 339-343

Andrew B. Kahng, Bao Liu: Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. ISVLSI 2003: 183-188

Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky: Engineering a scalable placement heuristic for DNA probe arrays. RECOMB 2003: 148-156

Andrew B. Kahng, Xu Xu: Accurate pseudo-constructive wirelength and congestion estimation. SLIP 2003: 61-68

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang: Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. SLIP 2003: 71-76

Alan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian: 2001 Technology Roadmap for Semiconductors. IEEE Computer 35(1): 42-53 (2002)

Andrew B. Kahng: Variability. IEEE Design & Test of Computers 19(3): 120, 116 (2002)

Andrew B. Kahng: The Road Ahead: The significance of packaging. IEEE Design & Test of Computers 19(6): 104-105 (2002)

Joshua N. Cooper, Robert B. Ellis, Andrew B. Kahng: Asymmetric Binary Covering Codes. J. Comb. Theory, Ser. A 100(2): 232-249 (2002)

Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Provably good global buffering by generalized multiterminalmulticommodity flow approximation. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 263-274 (2002)

Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky: Area fill synthesis for uniform layout density. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1132-1147 (2002)

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt: Toward better wireload models in the presence of obstacles. IEEE Trans. VLSI Syst. 10(2): 177-189 (2002)

Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven: Tools or users: which is the bigger bottleneck? DAC 2002: 76-77

Andrew B. Kahng, Bao Liu, Ion I. Mandoiu: Non-tree routing for reliability and yield improvement. ICCAD 2002: 260-266

C. Bandela, Yu Chen, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky: Auctions with Buyer Preferences. Information Systems: The e-Business Challenge 2002: 223-238

Andrew B. Kahng: A roadmap and vision for physical design. ISPD 2002: 112-117

Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky: Closing the smoothness and uniformity gap in area fill synthesis. ISPD 2002: 137-142

Andrew B. Kahng, Stefanus Mantik, Igor L. Markov: Min-max placement for large-scale timing optimization. ISPD 2002: 143-148

Andrew B. Kahng, Gary Smith: A New Design Cost Model for the 2001 ITRS (invited). ISQED 2002: 190-193

Andrew B. Kahng, Stefanus Mantik: Measurement of Inherent Noise in EDA Tools. ISQED 2002: 206-212

Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky: Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. VLSI Design 2002: 580-

Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky: Border Length Minimization in DNA Array Design. WABI 2002: 435-448

William H. Joyner Jr., Andrew B. Kahng: Guest Editor's Introduction: Roadmaps and Visions for Design and Test. IEEE Design & Test of Computers 18(6): 4-5 (2001)

Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt: Toward accurate models of achievable routing. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 648-659 (2001)

Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe: Constraint-based watermarking techniques for design IP protection. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1236-1252 (2001)

Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Provably good global buffering by multi-terminal multicommodity flow approximation. ASP-DAC 2001: 120-125

Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky: New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout. ASP-DAC 2001: 133-138

Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky: Hierarchical dummy fill for process uniformity. ASP-DAC 2001: 139-144

Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori: Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. ASP-DAC 2001: 267-268

Andrew B. Kahng: Design technology productivity in the DSM era (invited talk). ASP-DAC 2001: 443-448

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt: Toward better wireload models in the presence of obstacles. ASP-DAC 2001: 527-532

Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang: Panel: Is Nanometer Design Under Control? DAC 2001: 591-592

Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky: Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. ICCAD 2001: 408-

Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9

Andrew B. Kahng, Ronald Collett, Ton. H. van de Kraats: Design Metrics to Achieve Design Quality. ISQED 2001: 9

Andrew B. Kahng, Stefanus Mantik: A System for Automatic Recording and Prediction of Design Quality Metrics. ISQED 2001: 81-86

Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani: Noise Model for Multiple Segmented Coupled RC Interconnects. ISQED 2001: 145-150

Kenneth D. Boese, Andrew B. Kahng, Stefanus Mantik: On the relevance of wire load models. SLIP 2001: 91-98

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu: Interconnect implications of growth-based structural models for VLSI circuits. SLIP 2001: 99-106

Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Practical Approximation Algorithms for Separable Packing Linear Programs. WADS 2001: 325-337

Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning. ACM Journal of Experimental Algorithmics 5: 5 (2000)

Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky: Optimal phase conflict removal for layout of dark field alternatingphase shifting masks. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 175-187 (2000)

Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 267-272 (2000)

Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1304-1313 (2000)

Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky: Monte-Carlo algorithms for layout density control. ASP-DAC 2000: 523-528

Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Improved algorithms for hypergraph bipartitioning. ASP-DAC 2000: 661-666

Andrew B. Kahng, Sudhakar Muddu, Egino Sarto: On switch factor based analysis of coupled RC interconnects. DAC 2000: 79-84

Jennifer Smith, Tom Quan, Andrew B. Kahng: EDA meets.COM (panel session): how E-services will change the EDA business model. DAC 2000: 253

Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Can recursive bisection alone produce routable placements? DAC 2000: 477-482

Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky: Practical iterated fill synthesis for CMP uniformity. DAC 2000: 671-674

Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: GTX: the MARCO GSRC technology extrapolation system. DAC 2000: 693-698

Stephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges: METRICS: a system architecture for design process optimization. DAC 2000: 705-710

Andrew B. Kahng, Stefanus Mantik: On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. ICCAD 2000: 17-21

Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester: Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD 2000: 56-61

Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Provably Good Global Buffering Using an Available Buffer Block Plan. ICCAD 2000: 104-109

Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt: Requirements for models of achievable routing. ISPD 2000: 4-11

Andrew B. Kahng: Classical floorplanning harmful? ISPD 2000: 207-213

Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng: Admissibility Proofs for the LCS* Algorithm. IBERAMIA-SBIA 2000: 236-244

Andrew B. Kahng, Dirk Stroobandt: Wiring layer assignments with consistent stage delays. SLIP 2000: 115-122

Charles J. Alpert, Andrew B. Kahng, So-Zen Yao: Spectral Partitioning with Multiple Eigenvectors. Discrete Applied Mathematics 90(1-3): 3-26 (1999)

Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky: Filling algorithms and analyses for layout density control. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 445-462 (1999)

Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky: On wirelength estimations for row-based placement. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1265-1278 (1999)

Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. ALENEX 1999: 177-193

Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky: New Multilevel and Hierarchical Algorithms for Layout Density Control. ASP-DAC 1999: 221-224

Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov: Function Smoothing with Applications to VLSI Layout. ASP-DAC 1999: 225-

Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky: Optimization of Linear Placements for Wirelength Minimization with Free Sites. ASP-DAC 1999: 241-244

Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov: Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. DAC 1999: 349-354

Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hypergraph Partitioning with Fixed Vertices. DAC 1999: 355-359

Andrew B. Kahng, Y. C. Pati, Warren Grobman, Robert Pack, Lance A. Glasser: Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel). DAC 1999: 798

Andrew B. Kahng, Y. C. Pati: Subwavelength Lithography and Its Potential Impact on Design and EDA. DAC 1999: 799-804

Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong: Effective Iterative Techniques for Fingerprinting Design IP. DAC 1999: 843-848

Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky: The associative-skew clock routing problem. ICCAD 1999: 168-172

Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong: Copy detection for intellectual property protection of VLSI designs. ICCAD 1999: 600-605

Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Optimal partitioners and end-case placers for standard-cell layout. ISPD 1999: 90-96

Andrew B. Kahng, Y. C. Pati: Subwavelength optical lithography: challenges and impact on physical design. ISPD 1999: 112-119

Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky: Optimal phase conflict removal for layout of dark field alternating phase shifting masks. ISPD 1999: 121-126

Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Partitioning with terminals: a "new" problem and new benchmarks. ISPD 1999: 151-157

Andrew B. Kahng: Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications. VLSI Design 1999: 100-105

Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky: New and Exact Filling Algorithms for Layout Density Control. VLSI Design 1999: 106-110

Andrew B. Kahng, Sudhakar Muddu, Egino Sarto: Interconnect Optimization Strategies for High-Performance VLSI Designs. VLSI Design 1999: 464-469

Andrew B. Kahng, Sudhakar Muddu: Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. VLSI Design 1999: 578-583

Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Alexander Zelikovsky: The T-join Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout. WADS 1999: 25-36

Andrew B. Kahng, Gabriel Robins, Elizabeth A. Walkup: How to test a tree. Networks 32(3): 189-197 (1998)

Andrew B. Kahng, Majid Sarrafzadeh: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 1-2 (1998)

Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet: Faster minimization of linear wirelength for global placement. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 3-13 (1998)

Jason Cong, Andrew B. Kahng, Kwok-Shing Leung: Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 24-39 (1998)

Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng: Multilevel circuit partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 655-667 (1998)

Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998)

Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe: Watermarking Techniques for Intellectual Property Protection. DAC 1998: 776-781

Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe: Robust IP Watermarking Methodologies for Physical Design. DAC 1998: 782-787

Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma: Interconnect Tuning Strategies for High-Performance Ics. DATE 1998: 471-478

Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky: On wirelength estimations for row-based placement. ISPD 1998: 4-11

Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky: Filling and slotting: analysis and algorithms. ISPD 1998: 95-102

Andrew B. Kahng, Sudhakar Muddu: New efficient algorithms for computing effective capacitance. ISPD 1998: 147-151

Andrew B. Kahng: Futures for partitioning in physical design (tutorial). ISPD 1998: 190-193

Y. Uny Cao, Alex S. Fukunaga, Andrew B. Kahng: Cooperative Mobile Robotics: Antecedents and Directions. Auton. Robots 4(1): 7-27 (1997)

Inki Hong, Andrew B. Kahng, Byung Ro Moon: Improved Large-Step Markov Chain Variants for the Symmetric TSP. J. Heuristics 3(1): 63-81 (1997)

Lars W. Hagen, Andrew B. Kahng: Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 709-717 (1997)

Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng: On implementation choices for iterative improvement partitioning algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1199-1205 (1997)

Andrew B. Kahng, Sudhakar Muddu: An analytical delay model for RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1507-1514 (1997)

Andrew B. Kahng, Sudhakar Muddu: Analysis of RC interconnections under ramp input. ACM Trans. Design Autom. Electr. Syst. 2(2): 168-192 (1997)

Andrew B. Kahng, Chung-Wen Albert Tsao: Practical Bounded-Skew Clock Routing. VLSI Signal Processing 16(2-3): 199-215 (1997)

Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng: Multilevel Circuit Partitioning. DAC 1997: 530-533

Andrew B. Kahng, Chung-Wen Albert Tsao: More Practical Bounded-Skew Clock Routing. DAC 1997: 594-599

Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen: Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC 1997: 627-632

Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan: Faster minimization of linear wirelength for global placement. ISPD 1997: 4-11

Dennis J.-H. Huang, Andrew B. Kahng: Partitioning-based standard-cell global placement with an exact objective. ISPD 1997: 18-25

Jason Cong, Andrew B. Kahng, Kwok-Shing Leung: Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. ISPD 1997: 88-95

Andrew B. Kahng, Chung-Wen Albert Tsao: Planar-DME: a single-layer zero-skew clock tree router. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 8-19 (1996)

Charles J. Alpert, Andrew B. Kahng: A general framework for vertex orderings with applications to circuit clustering. IEEE Trans. VLSI Syst. 4(2): 240-246 (1996)

Andrew B. Kahng, Sudhakar Muddu: Analysis of RC Interconnections Under Ramp Input. DAC 1996: 533-538

Andrew B. Kahng, Kei Masuko, Sudhakar Muddu: Analytical delay models for VLSI interconnects under ramp input. ICCAD 1996: 30-36

T. C. Hu, Andrew B. Kahng, Chung-Wen Albert Tsao: Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting Methods. INFORMS Journal on Computing 7(4): 417-425 (1995)

Charles J. Alpert, Andrew B. Kahng: Recent directions in netlist partitioning: a survey. Integration 19(1-2): 1-81 (1995)

Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger: Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 890-896 (1995)

Charles J. Alpert, Andrew B. Kahng: Multiway partitioning via geometric embeddings, orderings, and dynamic programming. IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1342-1358 (1995)

Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins: Near-optimal critical sink routing tree constructions. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1417-1436 (1995)

Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng: Quantified Suboptimality of VLSI Layout Heuristics. DAC 1995: 216-221

Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao: On the Bounded-Skew Clock and Steiner Routing Problems. DAC 1995: 508-513

Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng: On implementation choices for iterative improvement partitioning algorithms. EURO-DAC 1995: 144-149

Dennis J.-H. Huang, Andrew B. Kahng: Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs. FPGA 1995: 140-145

Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71

Andrew B. Kahng, Byung Ro Moon: Toward More Powerful Recombinations. ICGA 1995: 96-103

Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran: On the intrinsic Rent parameter and spectra-based partitioning methodologies. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 27-37 (1994)

Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins: Rectilinear Steiner Trees with Minimum Elmore Delay. DAC 1994: 381-386

Andrew B. Kahng, Sudhakar Muddu: Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. DAC 1994: 563-569

Charles J. Alpert, Andrew B. Kahng: Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. DAC 1994: 652-657

Sudhakar Muddu, Andrew B. Kahng: Optimal equivalent circuits for interconnect delay calculations using moments. EURO-DAC 1994: 164-169

Chung-Wen Albert Tsao, Andrew B. Kahng: Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay. EURO-DAC 1994: 440-445

Charles J. Alpert, Andrew B. Kahng: A general framework for vertex orderings, with applications to netlist clustering. ICCAD 1994: 63-67

Andrew B. Kahng, Chung-Wen Albert Tsao: Low-cost single-layer clock trees with exact zero Elmore delay skew. ICCAD 1994: 213-218

Jason Cong, Andrew B. Kahng, Gabriel Robins: Matching-based methods for high-performance clock routing. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1157-1169 (1993)

Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins: High-Performance Routing Trees With Identified Critical Sinks. DAC 1993: 182-187

Charles J. Alpert, Andrew B. Kahng: Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. DAC 1993: 743-748

Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins: Fidelity and Near-Optimality of Elmore-Based Routing Constructions. ICCD 1993: 81-84

Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh: Minimum Density Interconneciton Trees. ISCAS 1993: 1865-1868

Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng: A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. ISCAS 1993: 1869-1872

Kenneth D. Boese, Andrew B. Kahng: Simulated annealing of neural networks: The 'cooling' strategy reconsidered. ISCAS 1993: 2572-2575

Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar: DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Design & Test of Computers 9(3): 7-20 (1992)

Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong: Provably good performance-driven global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 739-752 (1992)

Andrew B. Kahng, Gabriel Robins: A new class of iterative Steiner tree heuristics with good performance. IEEE Trans. on CAD of Integrated Circuits and Systems 11(7): 893-902 (1992)

Lars W. Hagen, Andrew B. Kahng: New spectral methods for ratio cut partitioning and clustering. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1074-1085 (1992)

Andrew B. Kahng, Gabriel Robins: On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension. IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1462-1465 (1992)

Jason Cong, Lars W. Hagen, Andrew B. Kahng: Net Partitions Yield Better Module Partitions. DAC 1992: 47-52

Lars W. Hagen, Andrew B. Kahng: A new approach to effective circuit clustering. ICCAD 1992: 422-427

Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen: An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158

Andrew B. Kahng, Gabriel Robins: Optimal algorithms for extracting spatial regularity in images. Pattern Recognition Letters 12(12): 757-764 (1991)

Andrew B. Kahng, Jason Cong, Gabriel Robins: High-Performance Clock Routing Based on Recursive Geometric Aatching. DAC 1991: 322-327

Lars W. Hagen, Andrew B. Kahng: Fast Spectral Methods for Ratio Cut Partitioning and Clustering. ICCAD 1991: 10-13

Andrew B. Kahng: An Effective Analog Approach to Steiner Routing. ICCD 1991: 166-169

Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong: Performance-Driven Global Routing for Cell Based ICs. ICCD 1991: 170-173

Andrew B. Kahng, Gabriel Robins: A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach. ICCAD 1990: 428-431

Andrew B. Kahng: Fast Hypergraph Partition. DAC 1989: 762-766