Nobuki Kajihara

Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara: Arithmetic Operation Oriented Reconfigurable Chip: RHW. FPL 2001: 618-622

Masaya Iwata, Isamu Kajitani, Yong Liu, Nobuki Kajihara, Tetsuya Higuchi: Implementation of a Gate-Level Evolvable Hardware Chip. ICES 2001: 38-49

Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara: Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. FCCM 2000: 281-282

Tetsuya Higuchi, Nobuki Kajihara: Evolvable Hardware Chips for Industrial Applications. Commun. ACM 42(4): 60-66 (1999)

Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi: The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. IEEE Trans. Computers 48(6): 628-639 (1999)

Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu: Real-world applications of analog and digital evolvable hardware . IEEE Trans. Evolutionary Computation 3(3): 220-235 (1999)

Isamu Kajitani, Tsutomu Hoshino, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi: An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller. AAAI/IAAI 1999: 182-187

Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi: Evolvable Hardware Chip for High Precision Printer Image Compression. AAAI/IAAI 1998: 486-491

Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi: A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. ICES 1998: 1-12

Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara: SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method. Parcella 1996: 128-136