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 | 2012 | |
|---|---|---|
| c28 |      | Jinpeng Lv, Priyank Kalla, Florian Enescu: Efficient Gröbner basis reductions for formal verification of galois field multipliers. DATE 2012: 899-904 |
| c27 | | Jinpeng Lv, Priyank Kalla: Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques. VLSI Design 2012: 388-393 |
| 2011 | ||
| c26 | | Christopher Condrat, Priyank Kalla, Steve Blair: Logic synthesis for integrated optics. ACM Great Lakes Symposium on VLSI 2011: 13-18 |
| c25 | | Jinpeng Lv, Priyank Kalla, Florian Enescu: Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques. HLDVT 2011: 136-143 |
| 2009 | ||
| j7 | | Sivaram Gopalakrishnan, Priyank Kalla: 2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra. ACM Trans. Design Autom. Electr. Syst. 14(4) (2009) |
| c24 | | Sivaram Gopalakrishnan, Priyank Kalla: Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis. DATE 2009: 1452-1457 |
| c23 | | |
| 2008 | ||
| j6 | | Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu: Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra. IEEE Trans. VLSI Syst. 16(4): 376-387 (2008) |
| c22 | | Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan: Verification of arithmetic datapaths using polynomial function models and congruence solving. ICCAD 2008: 122-128 |
| 2007 | ||
| j5 | | Sivaram Gopalakrishnan, Priyank Kalla: Optimization of polynomial datapaths using finite ring algebra. ACM Trans. Design Autom. Electr. Syst. 12(4) (2007) |
| c21 | | Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu: Optimization of Arithmetic Datapaths with Finite Word-Length Operands. ASP-DAC 2007: 511-516 |
| c20 | | Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu: Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors. ICCAD 2007: 143-148 |
| c19 | | Christopher Condrat, Priyank Kalla: A Gröbner Basis Approach to CNF-Formulae Preprocessing. TACAS 2007: 618-631 |
| 2006 | ||
| j4 | | Maciej J. Ciesielski, Priyank Kalla, Serkan Askar: Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. IEEE Trans. Computers 55(9): 1188-1201 (2006) |
| c18 | | Namrata Shekhar, Priyank Kalla, Florian Enescu: Equivalence verification of arithmetic datapaths with multiple word-length operands. DATE 2006: 824-829 |
| c17 | | Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu: Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands. FMCAD 2006: 179-186 |
| c16 | | Vijay Durairaj, Priyank Kalla: Guiding CNF-SAT Search by Analyzing Constraint-Variable Dependencies and Clause Lengths. HLDVT 2006: 155-161 |
| 2005 | ||
| c15 |  | Namrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan: Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra. ICCAD 2005: 291-296 |
| c14 | | Namrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu: Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths. ICCD 2005: 215-220 |
| c13 | | Vijay Durairaj, Priyank Kalla: Variable Ordering for Efficient SAT Search by Analyzing Constraint-Variable Dependencies. SAT 2005: 415-422 |
| 2004 | ||
| c12 | | Vijay Durairaj, Priyank Kalla: Dynamic analysis of constraint-variable dependencies to guide SAT diagnosis. HLDVT 2004: 135-140 |
| c11 | | Vijay Durairaj, Priyank Kalla: Exploiting hypergraph partitioning for efficient Boolean satisfiability. HLDVT 2004: 141-146 |
| c10 | | Vijay Durairaj, Priyank Kalla: Guiding CNF-SAT search via efficient constraint partitioning. ICCAD 2004: 498-501 |
| 2003 | ||
| c9 | | Sivaram Gopalakrishnan, Vijay Durairaj, Priyank Kalla: Integrating CNF and BDD based SAT solvers. HLDVT 2003: 51-56 |
| 2002 | ||
| j3 | | Priyank Kalla, Maciej J. Ciesielski: A comprehensive approach to the partial scan problem using implicitstate enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 810-826 (2002) |
| j2 | | Navin Vemuri, Priyank Kalla, Russell Tessier: BDD-based logic synthesis for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 501-525 (2002) |
| c8 | | Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-289 |
| c7 | | Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin: High-level design verification using Taylor Expansion Diagrams: first results. HLDVT 2002: 13-17 |
| 2001 | ||
| j1 | | Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski: Strategies for solving the Boolean satisfiability problem using binary decision diagrams. Journal of Systems Architecture 47(6): 491-503 (2001) |
| c6 | | Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski: LPSAT: a unified approach to RTL satisfiability. DATE 2001: 398-402 |
| c5 | | Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor expansion diagrams: a new representation for RTL verification. HLDVT 2001: 70-75 |
| 2000 | ||
| c4 | | Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang: A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. DATE 2000: 232-236 |
| 1999 | ||
| c3 | | Priyank Kalla, Maciej J. Ciesielski: Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. DATE 1999: 638-642 |
| 1998 | ||
| c2 | | Priyank Kalla, Maciej J. Ciesielski: A comprehensive approach to the partial scan problem using implicit state enumeration. ITC 1998: 651-657 |
| 1997 | ||
| c1 | | Priyank Kalla, Maciej J. Ciesielski: Testability of Sequential Circuits with Multi-Cycle False Path. VTS 1997: 322-328 |
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