Akihiro Kambe

List of publications from the DBLP Bibliography Server - FAQ
Other views: by type - by year (modern) - classic-C

Ask others: ACM DL/Guide -

	2012
j2		Masashi Kono, Akihiro Kambe, Hidehiro Toyoda, Shinji Nishimura: A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology. IEICE Transactions 95-B(11): 3437-3444 (2012)
	2011
j1		Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura: A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. J. Solid-State Circuits 46(12): 3101-3112 (2011)
c2		Masashi Kono, Akihiro Kambe, Hidehiro Toyoda: A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet. ICC 2011: 1-6
c1		Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura: 10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC 2011: 148-150

Coauthor Index

Last update Sat May 18 13:04:06 2013 CET by the DBLP Team —

Data released under the ODC-BY 1.0 license — See also our legal information page