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 | 2011 | |
|---|---|---|
| c19 |      | |
| 2008 | ||
| c18 | | Takashi Kambe, Makoto Saituji: A Variable Length Vector Pipeline Architecture Design Methodology. DSD 2008: 665-668 |
| 2006 | ||
| c17 | | Takashi Kambe, H. Matsuno, Y. Miyazaki, Akihisa Yamada: C-based design of a real time speech recognition system. ISCAS 2006 |
| 2001 | ||
| c16 | | Takashi Kambe, Akihisa Yamada, Koichi Nishida, Kazuhisa Okada, Mitsuhisa Ohnishi, Andrew Kay, Paul Boca, Vince Zammit, Toshio Nomura: A C-based synthesis system, Bach, and its application (invited talk). ASP-DAC 2001: 151-155 |
| 2000 | ||
| c15 | | Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe: Thread partitioning method for hardware compiler bach. ASP-DAC 2000: 303-308 |
| c14 | | Kazuhisa Okada, Takayuki Yamanouchi, Takashi Kambe: A cell synthesis method for salicide process. ASP-DAC 2000: 517-522 |
| 1999 | ||
| c13 | | Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada, Tetsuya Fujimoto, Takashi Kambe: A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler. ASP-DAC 1999: 193- |
| c12 | | Akihisa Yamada, Koichi Nishida, Ryoji Sakurai, Andrew Kay, Toshio Nomura, Takashi Kambe: Hardware synthesis with the Bach system. ISCAS (6) 1999: 366-369 |
| 1998 | ||
| j1 | | Akira Nagao, Isao Shirakawa, Takashi Kambe: A layout approach to monolithic microwave IC. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1262-1272 (1998) |
| c11 | | Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe: Binding and Scheduling Algorithms for Highly Retargetable Compilation. ASP-DAC 1998: 93-98 |
| c10 | | Akira Nagao, Takashi Kambe, Isao Shirakawa: A layout approach to monolithic microwave IC. ISPD 1998: 65-72 |
| 1997 | ||
| c9 | | Masayuki Yamaguchi, Akihisa Yamada, Toshihiro Nakaoka, Takashi Kambe: Architecture evaluation based on the datapath structure and parallel constraint. ASP-DAC 1997: 503-508 |
| c8 | | Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, Takashi Kambe: A method of redundant clocking detection and power reduction at RT level design. ISLPED 1997: 131-136 |
| 1996 | ||
| c7 | | Tetsuya Fujimoto, Takashi Kambe: VLSI Design and System Level Verification for the Mini-Disc. DAC 1996: 491-496 |
| c6 | | Takayuki Yamanouchi, Kazuo Tamakashi, Takashi Kambe: Hybrid floorplanning based on partial clustering and module restructuring. ICCAD 1996: 478-483 |
| 1995 | ||
| c5 | | Akira Nagao, Chiyoshi Yoshioka, Takashi Kambe, Isao Shirakawa: A layout approach to Monolithic Microwave IC. ASP-DAC 1995 |
| c4 |  | Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe: Optimal Scheduling for Conditional Recource Sharing. ISCAS 1995: 2297-2300 |
| 1993 | ||
| c3 | | Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Takashi Kambe: Optimal layout recycling based on graph theoretic linear programming approach. VLSI 1993: 25-34 |
| 1982 | ||
| c2 | | Takashi Kambe, Toru Chiba, Seiji Kimura, Tsuneo Inufushi, Noboru Okuda, Ikuo Nishioka: A placement algorithm for polycell LSI and ITS evaluation. DAC 1982: 655-662 |
| 1981 | ||
| c1 | | Toru Chiba, Noboru Okuda, Takashi Kambe, Ikuo Nishioka, Tsuneo Inufushi, Sieji Kimura: SHARPS: A hierarchical layout system for VLSI. DAC 1981: 820-827 |
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