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 | 2013 | |
|---|---|---|
| j50 |      | Martin Lukac, Michitaka Kameyama, Marek A. Perkowski: Quantum Finite State Machines - a Circuit Based Approach. IJUC 9(3-4): 267-301 (2013) |
| 2012 | ||
| j49 | | Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama: Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Transactions 95-D(2): 354-363 (2012) |
| j48 | | Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Transactions 95-C(8): 1434-1443 (2012) |
| j47 | | Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama: Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Transactions 95-C(12): 1872-1882 (2012) |
| j46 | | Xu Bai, Nobuaki Okada, Michitaka Kameyama: A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme. Multiple-Valued Logic and Soft Computing 20(1-2): 1-18 (2012) |
| j45 | | Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski: High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation? Multiple-Valued Logic and Soft Computing 20(1-2): 89-120 (2012) |
| c78 | | Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama: FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. ISCAS 2012: 1339-1342 |
| c77 | | Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS 2012: 3017-3020 |
| c76 | | Shogo Kisara, Michitaka Kameyama: Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits. ISMVL 2012: 104-109 |
| c75 | | Xu Bai, Michitaka Kameyama: Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture. ISMVL 2012: 208-213 |
| 2011 | ||
| j44 | | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Transactions 94-A(1): 342-351 (2011) |
| j43 | | Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Transactions 94-C(10): 1669-1679 (2011) |
| j42 | | Kan Watanabe, Masaru Fukushi, Michitaka Kameyama: Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing. JIP 19: 39-51 (2011) |
| j41 | | Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama: Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Techn. 21(10): 1453-1466 (2011) |
| j40 | | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. VLSI Syst. 19(8): 1394-1406 (2011) |
| c74 | | Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC 2011: 89-90 |
| c73 | | Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama: High Performance Tag Singulation for Memory-Less RFID Systems. ICC 2011: 1-6 |
| c72 | | Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama: Non-blocking tag scanning for passive RFID localization. ISDA 2011: 1140-1145 |
| c71 | | Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller: Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation. ISMVL 2011: 131-138 |
| i1 | | Maarti nLukac, Marek A. Perkowski, Michitaka Kameyama: Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics. CoRR abs/1107.3383 (2011) |
| 2010 | ||
| j39 | | Dalia Nashat, Xiaohong Jiang, Michitaka Kameyama: Group Testing Based Detection of Web Service DDoS Attackers. IEICE Transactions 93-B(5): 1113-1121 (2010) |
| j38 | | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Transactions 93-C(8): 1338-1348 (2010) |
| j37 | | |
| j36 | | Nobuaki Okada, Michitaka Kameyama: Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits. IEICE Transactions 93-D(8): 2126-2133 (2010) |
| j35 | | Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama: A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Transactions 93-D(8): 2134-2144 (2010) |
| j34 | | Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama: Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Transactions 93-A(12): 2570-2580 (2010) |
| c70 | | Martin Lukac, Marek A. Perkowski, Michitaka Kameyama: Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions. IEEE Congress on Evolutionary Computation 2010: 1-8 |
| c69 |  | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA 2010: 179-186 |
| c68 | | Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama: An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA 2010: 271-274 |
| c67 | | Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama: Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA 2010: 281-284 |
| c66 | | Martin Lukac, Michitaka Kameyama, Marek A. Perkowski: Adaptive Selection of Intelligent Processing Modules and its Applications. IC-AI 2010: 513-520 |
| c65 | | Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama: Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals. ISMVL 2010: 179-184 |
| 2009 | ||
| j33 | | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Transactions 92-C(4): 539-549 (2009) |
| j32 | | Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama: Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. IEEE Trans. VLSI Syst. 17(3): 403-416 (2009) |
| c64 | | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC 2009: 119-120 |
| c63 | | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA 2009: 145-150 |
| c62 | | Masanori Hariyama, Keita Tanji, Michitaka Kameyama: FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA 2009: 263-266 |
| c61 | | Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama: A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA 2009: 271-274 |
| c60 | | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA 2009: 291-294 |
| c59 | | Nobuaki Okada, Michitaka Kameyama: Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. ISMVL 2009: 54-59 |
| c58 | | Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama: Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. ISMVL 2009: 233-238 |
| 2008 | ||
| j31 | | Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama: Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. IEICE Transactions 91-C(4): 479-486 (2008) |
| j30 | | Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Transactions 91-C(4): 517-525 (2008) |
| j29 | | Masanori Hariyama, Shota Ishihara, Michitaka Kameyama: Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Transactions 91-C(9): 1419-1426 (2008) |
| j28 | | Nobuaki Okada, Michitaka Kameyama: Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation. IEICE Transactions 91-C(9): 1437-1443 (2008) |
| j27 | | Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama: Memory Allocation for Multi-Resolution Image Processing. IEICE Transactions 91-D(10): 2386-2397 (2008) |
| j26 | | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Transactions 91-A(12): 3596-3606 (2008) |
| c57 | | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama: Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA 2008: 201-207 |
| c56 | | Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama: Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA 2008: 309-310 |
| c55 | | Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama: FPGA implementation of a vehicle detection algorithm using three-dimensional information. IPDPS 2008: 1-5 |
| c54 | | Nobuaki Okada, Michitaka Kameyama: Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. ISMVL 2008: 180-185 |
| 2007 | ||
| j25 | | Michitaka Kameyama: Special Section on VLSI Technology toward Frontiers of New Market. IEICE Transactions 90-C(10): 1849 (2007) |
| j24 | | Tasuku Ito, Michitaka Kameyama: Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. Multiple-Valued Logic and Soft Computing 13(4-6): 553-568 (2007) |
| j23 | | Nobuaki Okada, Michitaka Kameyama: Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. Multiple-Valued Logic and Soft Computing 13(4-6): 619-632 (2007) |
| c53 | | Nobuaki Okada, Michitaka Kameyama: Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. ISMVL 2007: 25 |
| c52 | | Tasuku Ito, Michitaka Kameyama: Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. ISMVL 2007: 39 |
| 2006 | ||
| j22 | | Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama: Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. IEICE Transactions 89-C(11): 1551-1558 (2006) |
| j21 | | Masanori Hariyama, Sho Ogata, Michitaka Kameyama: A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. IEICE Transactions 89-C(11): 1655-1661 (2006) |
| c51 | | W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama: GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. APCCAS 2006: 1264-1267 |
| c50 | | Masanori Hariyama, Michitaka Kameyama: A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. APCCAS 2006: 1803-1806 |
| c49 | | Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama: Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. IPDPS 2006 |
| c48 | | Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama: Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. ISMVL 2006: 6 |
| c47 | | Haque Mohammad Munirul, Michitaka Kameyama: Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit. ISMVL 2006: 13 |
| c46 | | Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama: Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ISMVL 2006: 17 |
| c45 | | Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi: Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. ISVLSI 2006: 193-198 |
| 2005 | ||
| j20 | | Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama: Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. IEICE Transactions 88-D(7): 1486-1491 (2005) |
| j19 | | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. IEICE Transactions 88-A(12): 3298-3305 (2005) |
| j18 | | Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama: FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. IEICE Transactions 88-A(12): 3516-3522 (2005) |
| j17 | | Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama: Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. IEEE Trans. Computers 54(6): 642-650 (2005) |
| c44 | | Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama: Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. IPDPS 2005 |
| c43 | | Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi: VLSI architecture based on packet data transfer scheme and its application. ISCAS (2) 2005: 1786-1789 |
| c42 | | Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama: Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer. ISMVL 2005: 114-119 |
| c41 | | Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama: Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic. ISMVL 2005: 120-125 |
| c40 | | Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama: Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. ISVLSI 2005: 46-50 |
| 2004 | ||
| c39 | | Haque Mohammad Munirul, Michitaka Kameyama: Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic. ISMVL 2004: 26-30 |
| c38 | | Haque Mohammad Munirul, Michitaka Kameyama: Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. ISMVL 2004: 328-333 |
| c37 | | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama: Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ISVLSI 2004: 243-248 |
| c36 | | Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama: Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. ISVLSI 2004: 258-259 |
| 2003 | ||
| c35 | | Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama: Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. ISMVL 2003: 99-104 |
| c34 | | Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212 |
| 2002 | ||
| c33 | | Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL 2002: 161- |
| c32 | | Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Fully Source-Coupled Logic Based Multiple-Valued VLSI. ISMVL 2002: 270-275 |
| c31 | | Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama: High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. ISVLSI 2002: 95-100 |
| 2001 | ||
| c30 | | Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama: VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. ICRA 2001: 1168-1173 |
| c29 | | Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. ISMVL 2001: 21-26 |
| c28 | | Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, C. Zukeran: Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. ISMVL 2001: 167-172 |
| 2000 | ||
| j16 | | Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama: Architecture of a high-performance stereo vision VLSI processor. Advanced Robotics 14(5): 329-332 (2000) |
| c27 | | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ISMVL 2000: 382- |
| c26 | | Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL 2000: 423-429 |
| c25 | | Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama: Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438- |
| c24 | | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. PRDC 2000: 27-36 |
| 1999 | ||
| j15 | | Yoshichika Fujioka, Michitaka Kameyama: Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. Systems and Computers in Japan 30(12): 43-51 (1999) |
| c23 | | Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL 1999: 30-35 |
| c22 | | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1999: 275-279 |
| 1998 | ||
| j14 | | Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama: Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. Systems and Computers in Japan 29(11): 40-47 (1998) |
| j13 | | Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Systems and Computers in Japan 29(11): 48-54 (1998) |
| c21 | | Masanori Hariyama, Michitaka Kameyama: Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. ICRA 1998: 3691-3696 |
| c20 | | Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama: Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1998: 134-139 |
| c19 | | Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL 1998: 270-275 |
| 1997 | ||
| j12 | | Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama: A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. Systems and Computers in Japan 28(2): 54-61 (1997) |
| c18 | | Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama: Low-power multiple-valued current-mode integrated circuit with current-source control and its application. ASP-DAC 1997: 413-418 |
| c17 | | Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1997: 175- |
| 1996 | ||
| j11 | | Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi: Author's Reply. IEEE Trans. Computers 45(5): 639 (1996) |
| c16 | | Masami Nakajima, Michitaka Kameyama: Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. ISMVL 1996: 104-109 |
| c15 | | Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1996: 224-229 |
| 1995 | ||
| j10 | | Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. IEICE Transactions 78-D(8): 951-958 (1995) |
| c14 | | M. Ryu, Michitaka Kameyama: Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. ISMVL 1995: 20- |
| c13 | | Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64- |
| c12 | | Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ISMVL 1995: 92-97 |
| 1994 | ||
| j9 | | Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi: High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. IEEE Trans. Computers 43(1): 34-42 (1994) |
| c11 | | Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26 |
| c10 | | Masami Nakajima, Michitaka Kameyama: Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. ISMVL 1994: 223-230 |
| 1993 | ||
| j8 | | Shoui Kaqahito, Makoto Ishida, Tetsuro Nakamura, Kentaro Mizuno, Michitaka Kameyama, Tatsuo Higuchi: Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations. Systems and Computers in Japan 24(5): 40-52 (1993) |
| c9 | | Yoshichika Fujioka, Michitaka Kameyama: 2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. ICRA (3) 1993: 149-154 |
| c8 | | Masami Nakajima, Michitaka Kameyama: Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. ISMVL 1993: 283-288 |
| 1992 | ||
| j7 | | Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi: Interconnection-Free Biomolecular Computing. IEEE Computer 25(11): 41-50 (1992) |
| j6 | | Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi: Design of an ultrahigher-valued biocomputing system based on set-valued logic networks. Systems and Computers in Japan 23(7): 35-44 (1992) |
| c7 | | Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi: Design of a Multiple-Valued VLSI Processor for Digital Control. ISMVL 1992: 322-329 |
| c6 | | Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi: Residue Arithmetic Based Multiple-Valued VLSI Image Processor. ISMVL 1992: 330-336 |
| c5 | | Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi: Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. ISMVL 1992: 382-388 |
| 1991 | ||
| j5 | | Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi: Design of a robust fault-tolerant multiplier. Systems and Computers in Japan 22(2): 10-18 (1991) |
| j4 | | Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi: Performance evaluation of a multivalued rsa encryption vlsi. Systems and Computers in Japan 22(7): 12-21 (1991) |
| c4 | | Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi: High-Performance VLSI Processor for Robot Inverse Dynamics Computation. ICCD 1991: 608-611 |
| c3 | | Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi: Design of Interconnection-Free Biomolecular Computing System. ISMVL 1991: 173-180 |
| 1990 | ||
| c2 | | |
| c1 | | Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi: Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. ISMVL 1990: 355-362 |
| 1988 | ||
| j3 | | Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi: A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. IEEE Computer 21(4): 43-56 (1988) |
| 1977 | ||
| j2 | | Tatsuo Higuchi, Michitaka Kameyama: Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. IEEE Trans. Computers 26(12): 1212-1221 (1977) |
| j1 | | Michitaka Kameyama, Tatsuo Higuchi: Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. IEEE Trans. Computers 26(12): 1297-1302 (1977) |
Colors in the list of coauthors
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