| 2012 | ||
|---|---|---|
| c2 | Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong: A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. ISSCC 2012: 42-44 | |
| c1 | Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim: A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. ISSCC 2012: 48-50 | |
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