DBLP: Seokhyeong Kang

	2013
c10		Andrew B. Kahng, Seokhyeong Kang, Bongil Park: Active-mode leakage reduction with data-retained power gating. DATE 2013: 1209-1214
	2012
j1		Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 404-417 (2012)
c9		Andrew B. Kahng, Seokhyeong Kang: Accuracy-configurable adder for approximate arithmetic designs. DAC 2012: 820-825
c8		Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong: MAPG: Memory access power gating. DATE 2012: 1054-1059
c7		Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov: Sensitivity-guided metaheuristics for accurate discrete gate sizing. ICCAD 2012: 233-239
c6		Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong: TAP: token-based adaptive power gating. ISLPED 2012: 203-208
c5		Andrew B. Kahng, Seokhyeong Kang: Construction of realistic gate sizing benchmarks with known optimal solutions. ISPD 2012: 153-160
	2010
c4		Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC 2010: 825-831
c3		Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC 2010: 825-830
c2		Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA 2010: 1-11
c1		Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang: Toward effective utilization of timing exceptions in design optimization. ISQED 2010: 54-61

2013

c10

Andrew B. Kahng, Seokhyeong Kang, Bongil Park: Active-mode leakage reduction with data-retained power gating. DATE 2013: 1209-1214

2012

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 404-417 (2012)

Andrew B. Kahng, Seokhyeong Kang: Accuracy-configurable adder for approximate arithmetic designs. DAC 2012: 820-825

Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong: MAPG: Memory access power gating. DATE 2012: 1054-1059

Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov: Sensitivity-guided metaheuristics for accurate discrete gate sizing. ICCAD 2012: 233-239

Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong: TAP: token-based adaptive power gating. ISLPED 2012: 203-208

Andrew B. Kahng, Seokhyeong Kang: Construction of realistic gate sizing benchmarks with known optimal solutions. ISPD 2012: 153-160

2010

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC 2010: 825-831

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC 2010: 825-830

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA 2010: 1-11

Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang: Toward effective utilization of timing exceptions in design optimization. ISQED 2010: 54-61

1	Jin Hu	[c7]
2	Kwangok Jeong	[c8] [c1]
3	Andrew B. Kahng	[c10] [j1] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
4	Myung-Chul Kim	[c7]
5	Rakesh Kumar	[j1] [c4] [c3] [c2]
6	Igor L. Markov	[c7]
7	Bongil Park	[c10]
8	Tajana Rosing	[c6]
9	John Sartori	[j1] [c4] [c3] [c2]
10	Tajana Simunic (Tajana Simunic Rosing)	[c8]
11	Richard D. Strong	[c8] [c6]

Seokhyeong Kang

Coauthor Index