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 | 2010 | |
|---|---|---|
| c5 |      | Zohreh Karimi, Majid Sarrafzadeh: Fine-grained post placement voltage assignment considering level shifter overhead. VLSI-SoC 2010: 73-78 |
| 2009 | ||
| c4 | | Zohreh Karimi, Majid Sarrafzadeh: Power aware placement for FPGAs with dual supply voltages. ISQED 2009: 522-526 |
| 2007 | ||
| c3 | | Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh: Block placement to ensure channel routability. ACM Great Lakes Symposium on VLSI 2007: 465-468 |
| 2003 | ||
| c2 | | Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi: Utilizing Various ADL Facets for Instruction Level CPU Test. MTV 2003: 38- |
| c1 |  | Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi: Processor Testing Using an ADL Description and Genetic Algorithms. VLSI-SOC 2003: 186- |
| 1 | Maghsoud Abbaspour | |
| 2 | Shigetoshi Nakatake | |
| 3 | Zainalabedin Navabi | |
| 4 | Reihaneh Saberi | |
| 5 | Elham Safi | |
| 6 | Majid Sarrafzadeh | |
| 7 | Taraneh Taghavi |
Colors in the list of coauthors
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