Ramesh Karri

Garrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki: Hardware security strategies exploiting nanoelectronic circuits. ASP-DAC 2013: 368-372

Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri: Is split manufacturing secure? DATE 2013: 1259-1264

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu: Sneak-path Testing of Memristor-based Memories. VLSI Design 2013: 386-391

Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino: Leveraging Memristive Systems in the Construction of Digital Logic Circuits. Proceedings of the IEEE 100(6): 2033-2049 (2012)

Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose: An Energy-Efficient Memristive Threshold Logic Circuit. IEEE Trans. Computers 61(4): 474-487 (2012)

Miodrag Potkonjak, Ramesh Karri, Ingrid Verbauwhede, Kouichi Itoh: Guest Editorial Integrated Circuit and System Security. IEEE Transactions on Information Forensics and Security 7(1): 1-2 (2012)

Arun K. Kanuparthi, Mohamed Zahran, Ramesh Karri: Architecture Support for Dynamic Integrity Checking. IEEE Transactions on Information Forensics and Security 7(1): 321-332 (2012)

Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri: Security analysis of logic obfuscation. DAC 2012: 83-89

Xiaofei Guo, Ramesh Karri: Invariance-based concurrent error detection for advanced encryption standard. DAC 2012: 573-578

Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri: Logic encryption: A fault analysis perspective. DATE 2012: 953-958

Arun K. Kanuparthi, Ramesh Karri, Gaston Ormazabal, Sateesh Addepalli: A high-performance, low-overhead microarchitecture for secure program execution. ICCD 2012: 102-107

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu: Engineering crossbar based emerging memory technologies. ICCD 2012: 478-479

Jerry Backer, Ramesh Karri: Balancing performance and fault detection for GPGPU workloads. ICCD 2012: 518-519

Jeyavijayan Rajendran, Garrett S. Rose, Ramesh Karri, Miodrag Potkonjak: Nano-PPUF: A Memristor-Based Security Primitive. ISVLSI 2012: 84-87

Arun K. Kanuparthi, Ramesh Karri, Gaston Ormazabal, Sateesh Addepalli: A Survey of Microarchitecture Support for Embedded Processor Security. ISVLSI 2012: 368-373

Xiaofei Guo, Debdeep Mukhopadhyay, Ramesh Karri: Provably Secure Concurrent Error Detection Against Differential Fault Analysis. IACR Cryptology ePrint Archive 2012: 552 (2012)

Jeyavijayan Rajendran, Ramesh Karri, James Bradley Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki: Nanoelectronic Solutions for Hardware Security. IACR Cryptology ePrint Archive 2012: 575 (2012)

Wenjing Rao, Chengmo Yang, Ramesh Karri, Alex Orailoglu: Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge. IEEE Computer 44(2): 46-53 (2011)

Mohammad Tehranipoor, Hassan Salmani, Xuehui Zhang, Michel Wang, Ramesh Karri, Jeyavijayan Rajendran, Kurt Rosenfeld: Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges. IEEE Computer 44(7): 66-74 (2011)

Yu Liu, Kaijie Wu, Ramesh Karri: Scan-based attacks on linear feedback shift register based stream ciphers. ACM Trans. Design Autom. Electr. Syst. 16(2): 20 (2011)

Jeyavijayan Rajendran, Vinayaka Jyothi, Ramesh Karri: Blue team red team approach to hardware trust assessment. ICCD 2011: 285-288

Artem Durytskyy, Mohamed Zahran, Ramesh Karri: Improving GPU Robustness by making use of faulty parts. ICCD 2011: 346-351

Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose: Parallel memristors: Improving variation tolerance in memristive digital circuits. ISCAS 2011: 2241-2244

Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose: An Approach to Tolerate Process Related Variations in Memristor-Based Applications. VLSI Design 2011: 18-23

Kurt Rosenfeld, Ramesh Karri: Security-aware SoC test access mechanisms. VTS 2011: 100-104

Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri: Design and analysis of ring oscillator based Design-for-Trust technique. VTS 2011: 105-110

Ramesh Karri, Jeyavijayan Rajendran, Kurt Rosenfeld, Mohammad Tehranipoor: Trustworthy Hardware: Identifying and Classifying Hardware Trojans. IEEE Computer 43(10): 39-46 (2010)

Kurt Rosenfeld, Ramesh Karri: Attacks and Defenses for JTAG. IEEE Design & Test of Computers 27(1): 36-47 (2010)

Jeyavijayan Rajendran, Hetal Borad, Shyam Mantravadi, Ramesh Karri: SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers. HOST 2010: 70-75

Kurt Rosenfeld, Efstratios Gavas, Ramesh Karri: Sensor Physical Unclonable Functions. HOST 2010: 112-117

Arun K. Kanuparthi, Mohamed Zahran, Ramesh Karri: Feasibility study of dynamic Trusted Platform Module. ICCD 2010: 350-355

Jeyavijayan Rajendran, Efstratios Gavas, Jorge Jimenez, Vikram Padman, Ramesh Karri: Towards a comprehensive and systematic classification of hardware Trojans. ISCAS 2010: 1871-1874

Jianzhou Li, Ramesh Karri: Compact hardware architectures for BLAKE and LAKE hash functions. ISCAS 2010: 2107-2110

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Logic Mapping in Crossbar-Based Nanoarchitectures. IEEE Design & Test of Computers 26(1): 68-77 (2009)

Yu Liu, Kaijie Wu, Ramesh Karri: Scan-based Attacks on Linear Feedback Shift Register Based Stream Ciphers. IACR Cryptology ePrint Archive 2009: 584 (2009)

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Towards Nanoelectronics Processor Architectures. J. Electronic Testing 23(2-3): 235-254 (2007)

Kyosun Kim, Kaijie Wu, Ramesh Karri: The Robust QCA Adder Designs Using Composable QCA Building Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 176-183 (2007)

Bo Yang, Ramesh Karri: Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1763-1769 (2007)

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. DATE 2007: 865-869

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. DSN 2007: 216-224

Richard Stern, Nikhil Joshi, Kaijie Wu, Ramesh Karri: Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. FDTC 2007: 112-119

Kyosun Kim, Kaijie Wu, Ramesh Karri: Quantum-Dot Cellular Automata Design Guideline. IEICE Transactions 89-A(6): 1607-1614 (2006)

Bo Yang, Ramesh Karri, David A. McGrew: A High-Speed Hardware Architecture for Universal Message Authentication Code. IEEE Journal on Selected Areas in Communications 24(10): 1831-1839 (2006)

Nikhil Joshi, Jayachandran Sundararajan, Kaijie Wu, Bo Yang, Ramesh Karri: Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. IEEE Trans. Computers 55(10): 1230-1239 (2006)

Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Micropreemption synthesis: an enabling mechanism for multitask VLSI systems. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 19-30 (2006)

Kaijie Wu, Ramesh Karri: Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 413-422 (2006)

Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri: Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1163-1169 (2006)

Bo Yang, Kaijie Wu, Ramesh Karri: Secure Scan: A Design-for-Test Architecture for Crypto Chips. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2287-2293 (2006)

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Topology aware mapping of logic functions onto nanowire-based crossbar architectures. DAC 2006: 723-726

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. European Test Symposium 2006: 63-68

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. VTS 2006: 214-221

H. Wang, Malathi Veeraraghavan, Ramesh Karri, T. Li: Design of a High-Performance RSVP-TE Hardware Signaling Accelerator. IEEE Journal on Selected Areas in Communications 23(8): 1588-1595 (2005)

Bo Yang, Ramesh Karri, David A. McGrew: Divide-and-concatenate: an architecture-level optimization technique for universal hash functions. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1740-1747 (2005)

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault tolerant nanoelectronic processor architectures. ASP-DAC 2005: 311-316

Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu: Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. ASP-DAC 2005: 1192-1195

Bo Yang, Ramesh Karri: Power optimization for universal hash function data path using divide-and-concatenate technique. CODES+ISSS 2005: 219-224

Bo Yang, Kaijie Wu, Ramesh Karri: Secure scan: a design-for-test architecture for crypto chips. DAC 2005: 135-140

Kyosun Kim, Kaijie Wu, Ramesh Karri: owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. DATE 2005: 1214-1219

Bo Yang, Nikhil Joshi, Ramesh Karri: A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). FPGA 2005: 280

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. ICCD 2005: 533-542

Vitalij Ocheretnij, G. Kouznetsov, Ramesh Karri, Michael Gössel: On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations. IOLTS 2005: 141-146

Bo Yang, Sambit Mishra, Ramesh Karri: A High Speed Architecture for Galois/Counter Mode of Operation (GCM). IACR Cryptology ePrint Archive 2005: 146 (2005)

Darshan Sonecha, Bo Yang, Ramesh Karri, David A. McGrew: High speed architectures for Leviathan: a binary tree based stream cipher. Microprocessors and Microsystems 28(10): 573-584 (2004)

Kaijie Wu, Ramesh Karri: Fault secure datapath synthesis using hybrid time and hardware redundancy. IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1476-1485 (2004)

Inki Hong, Miodrag Potkonjak, Ramesh Karri: A heterogeneous built-in self-repair approach using system-level synthesis flexibility. IEEE Transactions on Reliability 53(1): 93-101 (2004)

Nikhil Joshi, Kaijie Wu, Ramesh Karri: Concurrent Error Detection Schemes for Involution Ciphers. CHES 2004: 400-412

Bo Yang, Ramesh Karri, David A. McGrew: Divide-and-concatenate: an architecture level optimization technique for universal hash functions. DAC 2004: 614-617

Bo Yang, Ramesh Karri, David A. McGrew: Divide and concatenate: a scalable hardware architecture for universal MAC. FPGA 2004: 258

Haobo Wang, Ramesh Karri, Malathi Veeraraghavan, Tao Li: A hardware-accelerated implementation of the RSVP-TE signaling protocol. ICC 2004: 1609-1614

Bo Yang, Kaijie Wu, Ramesh Karri: Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. ITC 2004: 339-344

Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. ITC 2004: 472-478

Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Low Cost Concurrent Error Detection for the Advanced Encryption Standard. ITC 2004: 1242-1248

Bo Yang, Kaijie Wu, Ramesh Karri: Scan Based Side Channel Attack on Data Encryption Standard. IACR Cryptology ePrint Archive 2004: 83 (2004)

Kaijie Wu, Piyush Mishra, Ramesh Karri: Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. Microelectronics Journal 34(1): 31-39 (2003)

Ramesh Karri, Piyush Mishra: Optimizing the Energy Consumed by Secure Wireless Sessions - Wireless Transport Layer Security Case Study. MONET 8(2): 177-185 (2003)

Kaijie Wu, Ramesh Karri: Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. IEEE Transactions on Reliability 52(4): 501-511 (2003)

Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers. CHES 2003: 113-124

Ramesh Karri, Piyush Mishra: An investigation into the design of energy-efficient session negotiation protocols for wireless networks. GLOBECOM 2003: 3488-3492

Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forrest Brewer, Kaustav Banerjee, Sankar Basu: Nano, quantum, and molecular computing: are we ready for the validation and test challenges? HLDVT 2003: 3-7

Ramesh Karri, Piyush Mishra: Modeling energy efficient secure wireless networks using network simulation. ICC 2003: 61-65

Kaijie Wu, Ramesh Karri: Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. ITC 2003: 902-911

Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Parity-Based Concurrent Error Detection in Symmetric Block Ciphers. ITC 2003: 919-926

Ramesh Karri, Piyush Mishra: Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks. PATMOS 2003: 358-368

Bo Yang, Ramesh Karri, David A. McGrew: Divide and Concatenate: A Scalable Hardware Architecture for Universal MAC. IACR Cryptology ePrint Archive 2003: 215 (2003)

Ramesh Karri, Balakrishnan Iyer, Israel Koren: Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 877-888 (2002)

Kaijie Wu, Ramesh Karri: Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1077-1087 (2002)

Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1509-1517 (2002)

Ramesh Karri, Kaijie Wu: Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. IEEE Trans. VLSI Syst. 10(6): 864-875 (2002)

Kaijie Wu, Ramesh Karri: Exploiting Idle Cycles for Algorithm Level Re-Computing. DATE 2002: 842-846

Ramesh Karri, Piyush Mishra: Minimizing energy consumption of secure wireless session with QoS constraints. ICC 2002: 2053-2057

Ramesh Karri: Guest editor's introduction to special section on high-level design validation and test. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 353-354 (2001)

Ramesh Karri, Balakrishnan Iyer: Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs. ACM Trans. Design Autom. Electr. Syst. 6(4): 505-515 (2001)

Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. DAC 2001: 579-585

Kaijie Wu, Ramesh Karri: Idle Cycles Based Concurrent Error Detection of RC6 Encryption. DFT 2001: 200-205

Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. DFT 2001: 427-435

Kaijie Wu, Ramesh Karri: Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. ICCAD 2001: 537-

Kaijie Wu, Ramesh Karri: Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. ITC 2001: 221-229

Ramesh Karri, Kyosun Kim, Miodrag Potkonjak: Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors. IEEE Trans. Computers 49(11): 1272-1284 (2000)

Ramesh Karri, Kaijie Wu: Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. ITC 2000: 971-978

Inki Hong, Miodrag Potkonjak, Ramesh Karri: Power optimization using divide-and-conquer techniques for minimization of the number of operations. ACM Trans. Design Autom. Electr. Syst. 4(4): 405-429 (1999)

Ramesh Karri, Michael Nicolaidis: Guest Editors' Introduction: Online VLSI Testing. IEEE Design & Test of Computers 15(4): 12-16 (1998)

Nilanjan Mukherjee, Ramesh Karri: Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures. J. Electronic Testing 13(2): 189-200 (1998)

Aurobindo Dasgupta, Ramesh Karri: High-reliability, low-energy microarchitecture synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1273-1280 (1998)

Inki Hong, Miodrag Potkonjak, Ramesh Karri: Heterogeneous BISR-approach using System Level Synthesis Flexibility. ASP-DAC 1998: 289-294

Ramesh Karri, Nilanjan Mukherjee: Versatile BIST: an integrated approach to on-line/off-line BIST. ITC 1998: 910-917

Miodrag Potkonjak, Kyosun Kim, Ramesh Karri: Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study. DAC 1997: 252-257

Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Synthesis of Application Specific Programmable Processors. DAC 1997: 353-358

Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems. ICCAD 1997: 33-38

Inki Hong, Miodrag Potkonjak, Ramesh Karri: Power optimization using divide-and-conquer techniques for minimization of the number of operations. ICCAD 1997: 108-111

Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, S. Roy, S. Wu: A Parameterized VHDL Library for On-Line Testing. ITC 1997: 479-488

Ramesh Karri, Karin Högstedt, Alex Orailoglu: Computer-Aided Design of Fault-Tolerant VLSI Systems. IEEE Design & Test of Computers 13(3): 88-96 (1996)

Alex Orailoglu, Ramesh Karri: Automatic Synthesis of Self-Recovering VLSI Systems. IEEE Trans. Computers 45(2): 131-142 (1996)

Balakrishnan Iyer, Ramesh Karri: Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis. DAC 1996: 137-142

Aurobindo Dasgupta, Ramesh Karri: Electromigration Reliability Enhancement via Bus Activity Distribution. DAC 1996: 353-356

Aurobindo Dasgupta, Ramesh Karri: Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing. DAC 1996: 819-824

Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Heterogeneous built-in resiliency of application specific programmable processors. ICCAD 1996: 406-411

Balakrishnan Iyer, Ramesh Karri, Israel Koren: Phantom redundancy: a high-level synthesis approach for manufacturability. ICCAD 1995: 658-661

Aurobindo Dasgupta, Ramesh Karri: Synthesis of Reliable Application Specific Heterogeneous Multiprocessors. ISCAS 1995: 1215-1218

Aurobindo Dasgupta, Ramesh Karri: Simultaneous scheduling and binding for power minimization during microarchitecture synthesis. ISLPD 1995: 69-74

Alex Orailoglu, Ramesh Karri: Synthesis of fault-tolerant and real-time microarchitectures. Journal of Systems and Software 25(1): 73-84 (1994)

Alex Orailoglu, Ramesh Karri: Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. IEEE Trans. VLSI Syst. 2(3): 304-311 (1994)

Ramesh Karri, Alex Orailoglu: Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. DAC 1994: 552-556

Sergei Sokolov, Ramesh Karri: Allocation and Binding During Fault-Secure Microarchitecture Synthesis. ICCD 1994: 327-330

Ramesh Karri, Alex Orailoglu: High-Level Synthesis of Fault-Secure Microarchitectures. DAC 1993: 429-433

Ramesh Karri, Alex Orailoglu: Optimal Self-Recovering Microarchitecture Synthesis. FTCS 1993: 512-521

Ramesh Karri, Alex Orailoglu: Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. DAC 1992: 662-665

Ramesh Karri, Alex Orailoglu: Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. FTCS 1992: 519-526

Alex Orailoglu, Ramesh Karri: High-Level Synthesis of Self-Recovering MicroArchitectures. ICCD 1992: 286-289

Ramesh Karri, Alex Orailoglu: ALPS: An Algorithm for Pipeline Data Path Synthesis. MICRO 1991: 124-132