Chandramouli V. Kashyap

Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 466-478 (2010)

Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm: Quantifying robustness metrics in parameterized static timing analysis. ICCAD 2009: 209-216

Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC 2008: 486-491

Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin: A "true" electrical cell model for timing, noise, and power grid verification. DAC 2008: 462-467

Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar: A framework for block-based timing sensitivity analysis. DAC 2008: 688-693

Chandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin: Silicon feedback to improve frequency of high-performance microprocessors: an overview. ICCAD 2008: 778-782

Kip Killpack, Chandramouli V. Kashyap, Eli Chiprout: Silicon Speedpath Measurement and Feedback into EDA flows. DAC 2007: 390-395

Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout: A nonlinear cell macromodel for digital applications. ICCAD 2007: 678-685

Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap: Fast Interconnect and Gate Timing Analysis for Performance Optimization. IEEE Trans. VLSI Syst. 14(12): 1383-1388 (2006)

Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout: A multi-port current source model for multiple-input switching effects in CMOS library cells. DAC 2006: 247-252

Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter: A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. DAC 2005: 186-189

Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004)

Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert: A delay metric for RC circuits based on the Weibull distribution. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 443-447 (2004)

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 509-516 (2004)

Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan: Closed-form delay and slew metrics made easy. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1661-1669 (2004)

Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan: Delay and slew metrics using the lognormal distribution. DAC 2003: 382-385

Anirudh Devgan, Chandramouli V. Kashyap: Block-based Static Timing Analysis with Uncertainty. ICCAD 2003: 607-614

Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter: Realizable reduction of RLC circuits using node elimination. ISCAS (3) 2003: 494-497

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD 2003: 24-31

Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert: A delay metric for RC circuits based on the Weibull distribution. ICCAD 2002: 620-624

Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter: Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) 2002: 197-200

Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 57-62

Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap: RC delay metrics for performance optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 571-582 (2001)

Chandramouli V. Kashyap, Byron Krauter: A realizable driving point model for on-chip interconnect with inductance. DAC 2000: 190-195

Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan: An "Effective" Capacitance Based Delay Metric for RC Interconnect. ICCAD 2000: 229-234

Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap: A two moment RC delay metric for performance optimization. ISPD 2000: 69-74