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Vinod Kathail
2010 – today
- 2010
[c11]Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro: Programming high performance signal processing systems in high level languages. FPGA 2010: 145- [e1]Vinod Kathail, Reid Tatge, Rajeev Barua (Eds.): Proceedings of the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2010, Scottsdale, AZ, USA, October 24-29, 2010. ACM 2010, ISBN 978-1-60558-903-9
2000 – 2009
- 2008
- [c10]
- 2007
- [c9]Vinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar: Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. VLSI Design 2007: 12
- 2002
- [j6]Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman: PICO: Automatically Designing Custom Computers. IEEE Computer 35(9): 39-47 (2002)
- [j5]Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman: PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. VLSI Signal Processing 31(2): 127-142 (2002)
- 2000
- [c8]Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider: High-Level Synthesis of Nonprogrammable Hardware Accelerators. ASAP 2000: 113-
1990 – 1999
- 1999
- [j4]B. Ramakrishna Rau, Vinod Kathail, Shail Aditya: Machine-Description Driven Compilers for EPIC and VLIW Processors. Design Autom. for Emb. Sys. 4(2-3): 71-118 (1999)
- [c7]Shail Aditya, B. Ramakrishna Rau, Vinod Kathail: Automatic Architectural Synthesis of VLIW and EPIC Processors. ISSS 1999: 107-113
- [c6]Hansoo Kim, Kanchi Gopinath, Vinod Kathail: Register allocation in hyper-block for EPIC processors. PARCO 1999: 550-557
- [c5]Hansoo Kim, Vinod Kathail, Kanchi Gopinath, Bhagirath Narahari: Fine Grained Register Allocation for EPIC Processors With Predication. PDPTA 1999: 2760-2766
- 1998
- [j3]Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich: Meld Scheduling: A Technique for Relaxing Scheduling Constraints. International Journal of Parallel Programming 26(4): 349-381 (1998)
- 1997
- [j2]Michael S. Schlansker, Vinod Kathail: Techniques for critical path reduction of scalar programs. International Journal of Parallel Programming 25(3): 147-181 (1997)
- 1996
- [j1]Michael S. Schlansker, Vinod Kathail, Sadun Anik: Parallelization of Control Recurrences for ILP Processors. International Journal of Parallel Programming 24(1): 65-102 (1996)
- [c4]Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich: Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. MICRO 1996: 308-321
- 1995
- [c3]Michael S. Schlansker, Vinod Kathail: Critical path reduction for scalar programs. MICRO 1995: 57-69
- 1994
- [c2]Michael S. Schlansker, Vinod Kathail, Sadun Anik: Height reduction of control recurrences for ILP processors. MICRO 1994: 40-51
- 1993
- [c1]Michael S. Schlansker, Vinod Kathail: Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. LCPC 1993: 406-429
Coauthor Index
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last updated on 2013-05-28 21:36 CEST by the dblp team