DBLP: Daniel Kehrer

	2010
j1		Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein: A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. J. Solid-State Circuits 45(1): 120-133 (2010)
	2009
c4		Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein: 75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. ISSCC 2009: 134-135
	2005
c3		Hans-Dieter Wohlmuth, Daniel Kehrer: A 24 GHz dual-modulus prescaler in 90nm CMOS. ISCAS (4) 2005: 3227-3230
	2004
c2		Hans-Dieter Wohlmuth, Daniel Kehrer: A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS. SBCCI 2004: 233-236
	2002
c1		W. Bakalski, Werner Simbürger, Daniel Kehrer, Hans-Dieter Wohlmuth, Mirjana Rest, Arpad L. Scholtz: A monolithic 2.45 GHz, 0.56 W power amplifier with 45% PAE at 2.4 V in standard 25 GHz f_T Si-bipolar. ISCAS (4) 2002: 803-806

2010

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein: A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. J. Solid-State Circuits 45(1): 120-133 (2010)

2009

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein: 75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. ISSCC 2009: 134-135

2005

Hans-Dieter Wohlmuth, Daniel Kehrer: A 24 GHz dual-modulus prescaler in 90nm CMOS. ISCAS (4) 2005: 3227-3230

2004

Hans-Dieter Wohlmuth, Daniel Kehrer: A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS. SBCCI 2004: 233-236

2002

W. Bakalski, Werner Simbürger, Daniel Kehrer, Hans-Dieter Wohlmuth, Mirjana Rest, Arpad L. Scholtz: A monolithic 2.45 GHz, 0.56 W power amplifier with 45% PAE at 2.4 V in standard 25 GHz f_T Si-bipolar. ISCAS (4) 2002: 803-806

1	W. Bakalski	[c1]
2	Ingo Bormann	[j1] [c4]
3	David Boursin	[j1] [c4]
4	Martin Brox	[j1] [c4]
5	Fabien Funfrock	[j1] [c4]
6	Mario Gjukic	[j1] [c4]
7	Peter Gregorius	[j1] [c4]
8	Thomas Hein	[j1] [c4]
9	Heinz Hoenigschmid	[j1] [c4]
10	Bianka Kho	[j1] [c4]
11	Rex Kho	[j1] [c4]
12	Sabine Kieser	[j1] [c4]
13	Maksim Kuzmenka	[j1] [c4]
14	Udo Moeller	[j1] [c4]
15	Pavel Veselinov Petkov	[j1] [c4]
16	Manfred Plan	[j1] [c4]
17	Mirjana Rest	[c1]
18	Michael Richter	[j1] [c4]
19	Ian Russell	[j1] [c4]
20	Kai Schiller	[j1] [c4]
21	Ronny Schneider	[j1] [c4]
22	Arpad L. Scholtz	[c1]
23	Werner Simbürger	[c1]
24	Wolfgang Spirkl	[j1] [c4]
25	Holger Steffens	[j1] [c4]
26	Kartik Swaminathan	[j1] [c4]
27	Bradley Weber	[j1] [c4]
28	Julien Weber	[j1] [c4]
29	Jörg Weller	[j1] [c4]
30	Hans-Dieter Wohlmuth	[c3] [c2] [c1]

Daniel Kehrer

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