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Martin Keim
2010 – today
- 2012
[c18]Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson: Re-using chip level DFT at board level. European Test Symposium 2012: 1
2000 – 2009
- 2008
- [c17]Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10
- [c16]Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann: Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data. ITC 2008: 1-9
- [c15]Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186
- 2007
- [c14]Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware: Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. European Test Symposium 2007: 145-150
- [c13]Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware: Silicon Evaluation of Static Alternative Fault Models. VTS 2007: 265-270
- 2006
- [c12]Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware: A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. ITC 2006: 1-10
- 2004
- [b1]
- [c11]Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski: Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC 2004: 1285-1294
- 2003
- [j3]Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor: Polynomial Formal Verification of Multipliers. Formal Methods in System Design 22(1): 39-58 (2003)
- 2002
- [c10]Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker: Sequential n -Detection Criteria: Keep It Simple. IOLTW 2002: 189
- 2001
- [j2]Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. J. Electronic Testing 17(1): 37-51 (2001)
1990 – 1999
- 1999
- [j1]Bernd Becker, Martin Keim, Rolf Krieger: Hybrid Fault Simulation for Synchronous Sequential Circuits. J. Electronic Testing 15(3): 219-238 (1999)
- [c9]Martin Keim, Nicole Drechsler, Bernd Becker: Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. ASP-DAC 1999: 315-318
- 1998
- [c8]Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. ISMVL 1998: 215-
- 1997
- [c7]Rolf Drechsler, Martin Keim, Bernd Becker: Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. ISMVL 1997: 66-
- [c6]Rolf Drechsler, Martin Keim, Bernd Becker: Fault Simulation in Sequential Multi-Valued Logic Networks. ISMVL 1997: 145-
- [c5]Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor: Polynomial Formal Verification of Multipliers. VTS 1997: 150-157
- [c4]Can Ökmen, Martin Keim, Rolf Krieger, Bernd Becker: On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms. VTS 1997: 426-433
- 1996
- [c3]Martin Keim, Bernd Becker, Birgitta Stenner: On the (non-)resetability of synchronous sequential circuits. VTS 1996: 240-245
- 1995
- [c2]Rolf Krieger, Bernd Becker, Martin Keim: Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy. DAC 1995: 339-344
- 1994
- [c1]Rolf Krieger, Bernd Becker, Martin Keim: A Hybrid Fault Simulator for Synchronous Sequential Circuits. ITC 1994: 614-623
Coauthor Index
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last updated on 2012-12-02 21:48 CET by the dblp team