Brion L. Keller

Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen: DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10

Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario H. Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel: Automation of 3D-DfT Insertion. Asian Test Symposium 2011: 395-400

Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki: Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Transactions 93-D(1): 17-23 (2010)

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise: Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC 2010: 724-733

Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller: CTL and Its Usage in the EDA Industry. IEEE Design & Test of Computers 26(1): 36-43 (2009)

Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai: Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electronics 5(4): 520-528 (2009)

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman: Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium 2009: 295-300

Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings: A Partially-Exhaustive Gate Transition Fault Model. Asian Test Symposium 2009: 361-364

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang: Capture power reduction using clock gating aware test generation. ITC 2009: 1-9

Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise: Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC 2007: 1-10

Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie: OCI: Open Compression Interface. ITC 2006: 1-4

Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi: Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium 2005: 156-161

Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman: Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium 2005: 470

Brion L. Keller, Thomas Bartenstein: Use of MISRs for compression and diagnostics. ITC 2005: 9

Vivek Chickermane, Brian Foutz, Brion L. Keller: Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC 2004: 452-461

Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane: An Economic Analysis and ROI Model for Nanometer Test. ITC 2004: 518-524

Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera: Extending OPMISR beyond 10x Scan Test Efficiency. IEEE Design & Test of Computers 19(5): 65-72 (2002)

Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater: A SmartBIST Variant with Guaranteed Encoding. Asian Test Symposium 2001: 325-

Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller: High Performance Parallel Fault Simulation. ICCD 2001: 308-313

Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay: CTL the language for describing core-based test. ITC 2001: 131-139

Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko: OPMISR: the foundation for compressed ATPG vectors. ITC 2001: 748-757

Paul Chang, Brion L. Keller, Sarala Paliwal: Effective parallel processing techniques for the generation of test data for a logic built-in self test system. Asian Test Symposium 2000: 374-379

Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton: Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. ITC 2000: 530-537

Paul Chang, Brion L. Keller, Sarala Paliwal: Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. ICCD 1999: 175-

Brion L. Keller: Using STIL to describe embedded core test requirements. ITC 1999: 1150

Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs: ATPG in practical and non-traditional applications. ITC 1998: 632-640

Pamela S. Gillis, Tom S. Guzowski, Brion L. Keller, Randal H. Kerr: Test methodologies and design automation for IBM ASICs. IBM Journal of Research and Development 40(4): 461-474 (1996)

Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams: Delay Test: The Next Frontier for LSSD Test Systems. ITC 1992: 578-587

Brion L. Keller, David P. Carlson, William Maloney: The Compiled Logic Simulator. IEEE Design & Test of Computers 8(1): 21-34 (1991)

Brion L. Keller, David A. Haynes: Design Automation of Test for the EX/9000^TM Series Processors. ICCD 1991: 550-553