| 2012 | ||
|---|---|---|
| c21 | WoeiTzy Jong, Hwei-Tseng Wang, Chengta Hsieh, Kei-Yong Khoo: ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite: CAD contest. ICCAD 2012: 342-344 | |
| 2008 | ||
| c20 | Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo: Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. DATE 2008: 813-818 | |
| 2006 | ||
| c19 | ||
| 2005 | ||
| c18 | Kei-Yong Khoo, Alan N. Willson Jr.: Efficient VLSI implementation of N/N integer division. ISCAS (1) 2005: 672-675 | |
| 2003 | ||
| j4 | Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.: Optimal joint module-selection and retiming with carry-save representation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 836-846 (2003) | |
| 2001 | ||
| j3 | Jason Cong, Jie Fang, Kei-Yong Khoo: DUNE-a multilayer gridless routing system. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 633-647 (2001) | |
| c17 | Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.: Design of optimal hybrid form FIR filter. ISCAS (2) 2001: 621-624 | |
| 2000 | ||
| j2 | Jason Cong, Jie Fang, Kei-Yong Khoo: Via design rule consideration in multilayer maze routing algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 215-223 (2000) | |
| c16 | Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.: The use of carry-save representation in joint module selection and retiming. DAC 2000: 768-773 | |
| c15 | Jason Cong, Jie Fang, Kei-Yong Khoo: DUNE: a multi-layer gridless routing system with wire planning. ISPD 2000: 12-18 | |
| 1999 | ||
| c14 | Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.: Bit-level arithmetic optimization for carry-save additions. ICCAD 1999: 14-19 | |
| c13 | Jason Cong, Jie Fang, Kei-Yong Khoo: An implicit connection graph maze routing algorithm for ECO routing. ICCAD 1999: 163-167 | |
| c12 | Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.: Improved-Booth encoding for low-power multipliers. ISCAS (1) 1999: 62-65 | |
| c11 | Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.: A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking. ISCAS (1) 1999: 298-301 | |
| c10 | Jason Cong, Jie Fang, Kei-Yong Khoo: VIA design rule consideration in multi-layer maze routing algorithms. ISPD 1999: 214-220 | |
| 1997 | ||
| c9 | Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. ICCAD 1997: 478-485 | |
| 1996 | ||
| c8 | Kei-Yong Khoo, Alan N. Willson Jr.: Cycle-Based Timing Simulations Using Event-Stream. ICCD 1996: 460- | |
| 1995 | ||
| j1 | Kei-Yong Khoo, Jason Cong: An efficient multilayer MCM router based on four-via routing. IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1277-1290 (1995) | |
| c7 | Kei-Yong Khoo, Alan N. Willson Jr.: Single-transistor transparent-latch clocking. ARVLSI 1995: 331-341 | |
| c6 | Chao-Liang Chen, Kei-Yong Khoo, Alan N. Willson Jr.: An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients. ISCAS 1995: 223-226 | |
| c5 | ||
| 1994 | ||
| c4 | ||
| 1993 | ||
| c3 | Kei-Yong Khoo, Jason Cong: An Efficient Multilayer MCM Router Based on Four-Via Routing. DAC 1993: 590-595 | |
| c2 | Kei-Yong Khoo, Alan Kwentus, Alan N. Willson Jr.: An efficient 175 MHz programmable FIR digital filter. ISCAS 1993: 72-75 | |
| 1991 | ||
| c1 | Jason Cong, Kei-Yong Khoo: A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. ICCD 1991: 319-322 | |
| 1 | Chao-Liang Chen | |
| 2 | Jason Cong | |
| 3 | Jie Fang | |
| 4 | Lei He | |
| 5 | Chengta Hsieh | |
| 6 | Chung-Yang Huang (Chung-Yang (Ric) Huang) | |
| 7 | WoeiTzy Jong | |
| 8 | Cheng-Kok Koh | |
| 9 | Alan Kwentus | |
| 10 | Chao-Yue Lai | |
| 11 | David Z. Pan (David Zhigang Pan) | |
| 12 | Hwei-Tseng Wang | |
| 13 | Alan N. Willson Jr. | |
| 14 | Zhan Yu |
Colors in the list of coauthors
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