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Hyesoon Kim
2010 – today
- 2012
[b1]Hyesoon Kim, Richard W. Vuduc, Sara S. Baghsorkhi, JeeWhan Choi, Wen-mei W. Hwu: Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU). Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2012- [j12]Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, Jinwoo Shin: DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function. Computer Architecture Letters 11(2): 33-36 (2012)
- [j11]Jaekyu Lee, Hyesoon Kim, Richard W. Vuduc: When Prefetching Works, When It Doesn't, and Why. TACO 9(1): 2 (2012)
- [c28]Jaekyu Lee, Hyesoon Kim: TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture. HPCA 2012: 91-102
- [c27]Minjang Kim, Pranith Kumar, Hyesoon Kim, Bevin Brett: Predicting Potential Speedup of Serial Code via Lightweight Profiling and Emulations with Memory Performance Model. IPDPS 2012: 1318-1329
- [c26]Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim: FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion. ISCA 2012: 321-332
- [c25]Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi: A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. MICRO 2012: 247-257
- [c24]Hyesoon Kim: Supporting virtual memory in GPGPU without supporting precise exceptions. MSPC 2012: 70-71
- [c23]
- [c22]Jaewoong Sim, Aniruddha Dasgupta, Hyesoon Kim, Richard W. Vuduc: A performance analysis framework for identifying potential benefits in GPGPU applications. PPOPP 2012: 11-22
- 2010
- [c21]Dongwon Lee, Marilyn Wolf, Hyesoon Kim: Design space exploration of the turbo decoding algorithm on GPUs. CASES 2010: 217-226
- [c20]
- [c19]Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard W. Vuduc: Many-Thread Aware Prefetching Mechanisms for GPGPU Applications. MICRO 2010: 213-224
- [c18]Minjang Kim, Hyesoon Kim, Chi-Keung Luk: SD3: A Scalable Approach to Dynamic Data-Dependence Profiling. MICRO 2010: 535-546
2000 – 2009
- 2009
- [j10]Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn: Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware. IEEE Trans. Computers 58(9): 1153-1170 (2009)
- [c17]Sunpyo Hong, Hyesoon Kim: An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness. ISCA 2009: 152-163
- [c16]Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim: Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping. MICRO 2009: 45-55
- [c15]Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim: Age based scheduling for asymmetric multiprocessors. SC 2009
- 2008
- [c14]José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt: Improving the performance of object-oriented languages with dynamic predication of indirect jumps. ASPLOS 2008: 80-90
- [c13]Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt: Performance-aware speculation control using wrong path usefulness prediction. HPCA 2008: 39-49
- [c12]Nagesh B. Lakshminarayana, Hyesoon Kim: Understanding performance, power and energy behavior in asymmetric multiprocessors. ICCD 2008: 471-477
- 2007
- [j9]José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt: Dynamic Predication of Indirect Jumps. Computer Architecture Letters 6(2): 25-28 (2007)
- [j8]José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt: Dynamic Predication of Indirect Jumps. Computer Architecture Letters 7(1): 1-4 (2007)
- [j7]Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. IEEE Micro 27(1): 94-104 (2007)
- [c11]Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. CGO 2007: 367-378
- [c10]Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt: Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. HPCA 2007: 63-74
- [c9]Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn: VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA 2007: 424-435
- 2006
- [j6]Onur Mutlu, Hyesoon Kim, Yale N. Patt: Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. IEEE Micro 26(1): 10-20 (2006)
- [j5]Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark: Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. IEEE Micro 26(1): 48-58 (2006)
- [j4]Onur Mutlu, Hyesoon Kim, Yale N. Patt: Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. IEEE Trans. Computers 55(12): 1491-1508 (2006)
- [c8]Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt: 2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. CGO 2006: 159-172
- [c7]Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. MICRO 2006: 53-64
- 2005
- [j3]Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt: On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. Computer Architecture Letters 4(1): 2 (2005)
- [j2]Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. International Journal of Parallel Programming 33(5): 529-559 (2005)
- [j1]Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. IEEE Trans. Computers 54(12): 1556-1571 (2005)
- [c6]Onur Mutlu, Hyesoon Kim, Yale N. Patt: Techniques for Efficient Processing in Runahead Execution Engines. ISCA 2005: 370-381
- [c5]Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt: Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. MICRO 2005: 43-54
- [c4]Onur Mutlu, Hyesoon Kim, Yale N. Patt: Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. MICRO 2005: 233-244
- 2004
- [c3]David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt: Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. MICRO 2004: 119-128
- [c2]Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. SBAC-PAD 2004: 2-9
- [c1]Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Understanding the effects of wrong-path memory references on processor performance. WMPI 2004: 56-64
Coauthor Index
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last updated on 2013-04-11 18:45 CEST by the dblp team