| 2011 | ||
|---|---|---|
| j3 | Chi-Li Yu, Jungsub Kim, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti: FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data. Signal Processing Systems 64(1): 109-122 (2011) | |
| 2009 | ||
| j2 | Jungsub Kim, Lanping Deng, Prasanth Mangalagiri, Kevin M. Irick, Kanwaldeep Sobti, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun: An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. IEEE Trans. Computers 58(12): 1654-1667 (2009) | |
| j1 | Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu: Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. IEEE Trans. Dependable Sec. Comput. 6(3): 202-216 (2009) | |
| c5 | Jungsub Kim, Chi-Li Yu, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti: FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data. SiPS 2009: 121-126 | |
| 2008 | ||
| c4 | Lanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jungsub Kim, Vijaykrishnan Narayanan: Efficient image reconstruction using partial 2D Fourier transform. SiPS 2008: 49-54 | |
| 2007 | ||
| c3 | Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun: TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. FPL 2007: 68-73 | |
| c2 | Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun, Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan: Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations. SiPS 2007: 463-468 | |
| 2006 | ||
| c1 | R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design 2006: 499-502 | |
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