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 | 2012 | |
|---|---|---|
| c1 |      | Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong: A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. ISSCC 2012: 42-44 |
| 1 | Mi-Hyun Cho | |
| 2 | Woong-Ju Jang | |
| 3 | Byung-Tae Jeong | |
| 4 | Jong-Ho Kang | |
| 5 | Dong-Whee Kim | |
| 6 | Hyungsoo Kim | |
| 7 | Kang-Yeol Lee | |
| 8 | Kyu-Nam Lim | |
| 9 | Keun-Woo Park | |
| 10 | Hyung-Sik Won |
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