Yong-Bin Kim

Tina Marie Rookmaaker, Moon Seok Kim, Yong-Bin Kim: Design and analysis of the quadfferential amplifier. Microelectronics Journal 43(10): 697-707 (2012)

In-Seok Jung, Yong-Bin Kim: A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter. IEEE Transactions on Industrial Electronics 59(2): 1154-1160 (2012)

Jianping Gong, Yong-Bin Kim, Fabrizio Lombardi, Jie Han: Hardening a memory cell for low power operation by gate leakage reduction. DFT 2012: 73-78

HeungJun Jeon, Yong-Bin Kim: A fully integrated switched-capacitor DC-DC converter with dual output for low power application. ACM Great Lakes Symposium on VLSI 2012: 83-86

In-Seok Jung, Yong-Bin Kim: A low stand-by power start-up circuit for SMPS PWM controller. ACM Great Lakes Symposium on VLSI 2012: 251-254

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi: A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. IEEE Trans. VLSI Syst. 19(5): 900-904 (2011)

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi: Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. ICCD 2011: 320-325

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi: Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integration 43(2): 176-187 (2010)

HeungJun Jeon, Yong-Bin Kim, Minsu Choi: Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems. IEEE T. Instrumentation and Measurement 59(5): 1127-1133 (2010)

Jun Zhao, Yong-Bin Kim: A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops. VLSI Design 2010 (2010)

Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi: 8Gb/s capacitive low power and high speed 4-PWAM transceiver design. ACM Great Lakes Symposium on VLSI 2010: 33-38

HeungJun Jeon, Yong-Bin Kim: A low-offset high-speed double-tail dual-rail dynamic latched comparator. ACM Great Lakes Symposium on VLSI 2010: 45-48

Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi: Performance assessment of analog circuits with carbon nanotube FET (CNFET). ACM Great Lakes Symposium on VLSI 2010: 163-166

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi: Read-out schemes for a CNTFET-based crossbar memory. ACM Great Lakes Symposium on VLSI 2010: 167-170

Jun Wu, Yong-Bin Kim, Minsu Choi: Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. ACM Great Lakes Symposium on VLSI 2010: 459-464

Jun Zhao, Yong-Bin Kim: A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur. ISQED 2010: 99-102

Young Bok Kim, Yong-Bin Kim: High speed and low power transceiver design with CNFET and CNT bundle interconnect. SoCC 2010: 152-157

Jiaping Hu, Yong-Bin Kim, Joseph Ayers: A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier. SoCC 2010: 281-284

HeungJun Jeon, Yong-Bin Kim: A CMOS low-power low-offset and high-speed fully dynamic latched comparator. SoCC 2010: 285-288

Cristiana Bolchini, Yong-Bin Kim: Guest Editorial. J. Electronic Testing 25(1): 9-10 (2009)

Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi: A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates. IEEE T. Instrumentation and Measurement 58(2): 401-410 (2009)

Kyung Ki Kim, Yong-Bin Kim: A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems. IEEE Trans. VLSI Syst. 17(4): 517-528 (2009)

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi: A Novel Hardened Design of a CMOS Memory Cell at 32nm. DFT 2009: 58-64

Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi: Errors in DNA Self-Assembly by Synthesized Tile Sets. DFT 2009: 112-120

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi: Soft-Error Hardening Designs of Nanoscale CMOS Latches. VTS 2009: 41-46

Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi: Monomer Control for Error Tolerance in DNA Self-Assembly. J. Electronic Testing 24(1-3): 271-284 (2008)

Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi: Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels. IEEE Trans. Industrial Informatics 4(2): 134-143 (2008)

Stephen Frechette, Yong-Bin Kim, Fabrizio Lombardi: Checkpointing of Rectilinear Growth in DNA Self-Assembly. DFT 2008: 525-533

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi: A low leakage 9t sram cell for ultra-low power operation. ACM Great Lakes Symposium on VLSI 2008: 123-126

Jun Zhao, Yong-Bin Kim: A low power 32 nanometer CMOS digitally controlled oscillator. SoCC 2008: 183-186

Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi: Low power 8T SRAM using 32nm independent gate FinFET technology. SoCC 2008: 247-250

Cristiana Bolchini, Yong-Bin Kim, Dimitris Gizopoulos, Mohammad Tehranipoor (Eds.): 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA. IEEE Computer Society 2008

Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park: Leakage Minimization Technique for Nanoscale CMOS VLSI. IEEE Design & Test of Computers 24(4): 322-330 (2007)

Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin Kim, Joseph Ayers: Low power CMOS electronic central pattern generator design for a biomimetic underwater robot. Neurocomputing 71(1-3): 284-296 (2007)

Leonid Zamdborg, Richard D. LeDuc, Kevin J. Glowacz, Yong-Bin Kim, Vinayak Viswanathan, Ian T. Spaulding, Bryan P. Early, Eric J. Bluhm, Shannee Babai, Neil L. Kelleher: ProSight PTM 2.0: improved protein identification and characterization for top down mass spectrometry. Nucleic Acids Research 35(Web-Server-Issue): 701-706 (2007)

Young Bok Kim, Yong-Bin Kim: Fault Tolerant Source Routing for Network-on-Chip. DFT 2007: 12-20

Ravi Bonam, Yong-Bin Kim, Minsu Choi: Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. DFT 2007: 161-169

Yong-Bin Kim, Kyung Ki Kim, James T. Doyle: A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control. ISCAS 2007: 1149-1152

Kyung Ki Kim, Yong-Bin Kim: Optimal Body Biasing for Minimum Leakage Power in Standby Mode. ISCAS 2007: 1161-1164

Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba (Eds.): 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. IEEE Computer Society 2007, isbn 0-7695-2885-6

Jihyun Lee, Yong-Bin Kim: ASLIC: A low power CMOS analog circuit design automation. Integration 39(3): 157-181 (2006)

Rui Tang, Fengming Zhang, Yong-Bin Kim: Design metal-dot based QCA circuits using SPICE model. Microelectronics Journal 37(8): 821-827 (2006)

Luca Schiano, Mariam Momenzadeh, Fengming Zhang, Young-Jun Lee, Thomas Kane, Solomon Max, Philip Perkins, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer: Measuring the timing jitter of ATE in the frequency domain. IEEE T. Instrumentation and Measurement 55(1): 280-289 (2006)

Marco Ottavi, Luca Schiano, Xiaopeng Wang, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi: Evaluating the Yield of Repairable SRAMs for ATE. IEEE T. Instrumentation and Measurement 55(5): 1704-1712 (2006)

Woon Kang, Yong-Bin Kim, T. Doyle: A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine. IEEE Trans. VLSI Syst. 14(3): 229-240 (2006)

Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi: Error Tolerance of DNA Self-Assembly by Monomer Concentration Control. DFT 2006: 89-97

Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim: Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects. DFT 2006: 98-106

Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi: Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations. DFT 2006: 486-494

Rui Tang, Yong-Bin Kim: PWAM signalling scheme for high speed serial link transceiver design. ACM Great Lakes Symposium on VLSI 2006: 49-52

Rui Tang, Yong-Bin Kim: A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits. SoCC 2006: 119-122

Fengming Zhang, Rui Tang, Yong-Bin Kim: SET-based nano-circuit simulation and design method using HSPICE. Microelectronics Journal 36(8): 741-748 (2005)

Noh-Jin Park, K. M. George, Nohpill Park, Minsu Choi, Yong-Bin Kim, Fabrizio Lombardi: Environmental-based characterization of SoC-based instrumentation systems for stratified testing. IEEE T. Instrumentation and Measurement 54(3): 1241-1248 (2005)

Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi: On the Modeling and Analysis of Jitter in ATE Using Matlab. DFT 2005: 285-293

Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi: Data Dependent Jitter (DDJ) Characterization Methodology. DFT 2005: 294-304

Rui Tang, Fengming Zhang, Yong-Bin Kim: Quantum-dot cellular automata SPICE macro model. ACM Great Lakes Symposium on VLSI 2005: 108-111

Rui Tang, Fengming Zhang, Yong-Bin Kim: QCA-based nano circuits design [adder design example]. ISCAS (3) 2005: 2527-2530

Jihyun Lee, Yong-Bin Kim: ASLIC: A Low Power CMOS Analog Circuit Design Automation. ISQED 2005: 470-475

Minsu Choi, Nohpill Park, Vincenzo Piuri, Yong-Bin Kim, Fabrizio Lombardi: Balanced dual-stage repair for dependable embedded memory cores. Journal of Systems Architecture 50(5): 281-285 (2004)

James T. Doyle, Young-Jun Lee, Yong-Bin Kim: Fast and accurate DAC modeling techniques based on wavelet theory. Microelectronics Journal 35(5): 451-460 (2004)

Richard D. LeDuc, Gregory K. Taylor, Yong-Bin Kim, Thomas E. Januszyk, Lee H. Bynum, Joseph V. Sola, John S. Garavelli, Neil L. Kelleher: ProSight PTM: an integrated environment for protein identification and characterization by top-down mass spectrometry. Nucleic Acids Research 32(Web-Server-Issue): 340-345 (2004)

T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi: Fault tolerant clockless wave pipeline design. Conf. Computing Frontiers 2004: 350-356

Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi: Scan Test of IP Cores in an ATE Environment. DELTA 2004: 281-286

T. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer: Reliability Modeling and Assurance of Clockless Wave Pipeline. DFT 2004: 442-450

Fengming Zhang, Rui Tang, Yong-Bin Kim: SET-based nano-circuit simulation and design method using HSPICE. ACM Great Lakes Symposium on VLSI 2004: 344-347

Young-Jun Lee, Jihyun Lee, Yong-Bin Kim, Joseph Ayers, Alexander Volkovskii, Allen I. Selverston, Henry D. I. Abarbanel, Mikhail I. Rabinovich: Low power real time electronic neuron VLSI design using subthreshold technique. ISCAS (4) 2004: 744-747

Young-Jun Lee, Yong-Bin Kim: A fast and precise interconnect capacitive coupling noise model. ISCAS (2) 2004: 873-876

Jihyun Lee, Young-Jun Lee, Yong-Bin Kim: SRAM word-oriented redundancy methodology using built in self-repair. SoCC 2004: 219-222

Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi: Guest Editors' Introduction: Clockless VLSI Systems. IEEE Design & Test of Computers 20(6): 5-8 (2003)

Woo Jin Kim, Yong-Bin Kim: Automating Wave-Pipelined Circuit Design. IEEE Design & Test of Computers 20(6): 51-58 (2003)

Young-Jun Lee, Thomas Kane, Jong-Jin Lim, Young Jun Schiano, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, Solomon Max: Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment. IEEE T. Instrumentation and Measurement 52(6): 1749-1755 (2003)

T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri: Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. DFT 2003: 34-

Fengming Zhang, Young-Jun Lee, Thomas Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, Solomon Max, Phil Perkinson: A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment. DFT 2003: 159-166

Yeshwant Kolla, Yong-Bin Kim, John Carter: A novel 32-bit scalable multiplier architecture. ACM Great Lakes Symposium on VLSI 2003: 241-244

Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim: A Novel Clocking Strategy for Dynamic Circuits. ISQED 2003: 307-312

Minsu Choi, Hardy J. Pottinger, Nohpill Park, Yong-Bin Kim: Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems. MSE 2003: 121-122

Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri: Optimal Spare Utilization in Repairable and Reliable Memory Cores. MTDT 2003: 64-71

Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi: Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. NCA 2003: 341-

Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park: A Test-Vector Generation Methodology for Crosstalk Noise Faults. DFT 2002: 40-50

Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri: Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. DFT 2002: 419-427

Dae Woon Kang, Yong-Bin Kim: Design flow of robust routed power distribution for low power ASIC. ISCAS (1) 2002: 181-184

Minsu Choi, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi: Hardware/Software Co-Reliability of Configurable Digital Systems. PRDC 2002: 67-74

Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel: Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. ARVLSI 2001: 132-147

Yong-Bin Kim, Tom Chen: A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps. ASP-DAC 1997: 681-682