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Kozo Kinoshita
2010 – today
- 2010
[c65]Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita: Current-based testable design of level shifters in liquid crystal display drivers. European Test Symposium 2010: 262
2000 – 2009
- 2008
- [j47]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electronic Testing 24(4): 379-391 (2008)
- 2007
- [j46]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita: A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Transactions 90-D(9): 1398-1405 (2007)
- [j45]Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita: A statistical error model for image sensors and its testing. Systems and Computers in Japan 38(11): 1-11 (2007)
- 2006
- [j44]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Transactions 89-D(5): 1679-1686 (2006)
- [j43]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita: A Per-Test Fault Diagnosis Method Based on the X-Fault Model. IEICE Transactions 89-D(11): 2756-2765 (2006)
- [c64]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita: A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS 2006: 58-65
- 2005
- [j42]Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita: Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. J. Electronic Testing 21(6): 613-620 (2005)
- [j41]Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. IEICE Transactions 88-D(4): 703-710 (2005)
- [j40]Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: Fault Diagnosis of Physical Defects Using Unknown Behavior Model. J. Comput. Sci. Technol. 20(2): 187-194 (2005)
- [c63]Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: Low-capture-power test generation for scan-based at-speed testing. ITC 2005: 10
- [c62]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: On Low-Capture-Power Test Generation for Scan Testing. VTS 2005: 265-270
- 2004
- [c61]Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita: On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. DELTA 2004: 269-274
- [c60]Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: On per-test fault diagnosis using the X-fault model. ICCAD 2004: 633-640
- 2003
- [c59]Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita: Reducing Scan Shifts Using Folding Scan Trees. Asian Test Symposium 2003: 6-11
- [c58]Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: Fault Diagnosis for Physical Defects of Unknown Behaviors. Asian Test Symposium 2003: 236-241
- [c57]Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita: A BIST Circuit for IDDQ Tests. Asian Test Symposium 2003: 390-395
- [c56]Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa: Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. VLSI Design 2003: 329-334
- 2002
- [j39]
- [j38]Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita: Built-in Self-Test for crosstalk faults in a digital VLSI. Systems and Computers in Japan 33(13): 35-47 (2002)
- [c55]Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita: Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. Asian Test Symposium 2002: 176-181
- [c54]Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita: Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. DELTA 2002: 92-98
- [c53]Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita: On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC 2002: 83-89
- 2001
- [c52]Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita: IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium 2001: 111-116
- [c51]Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita: Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits. Asian Test Symposium 2001: 469
- 2000
- [j37]Toshiyuki Maeda, Kozo Kinoshita: Compaction of IDDQ Test Sequence Using Reassignment Method. J. Electronic Testing 16(3): 243-249 (2000)
- [j36]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electronic Testing 16(5): 443-451 (2000)
- [j35]Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita: Static test compaction for IDDQ testing of bridging faults in sequential circuits. Systems and Computers in Japan 31(11): 41-50 (2000)
- [c50]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC 2000: 509-514
- [c49]Arabi Keshk, Yukiya Miura, Kozo Kinoshita: Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. Asian Test Symposium 2000: 120-124
- [c48]Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita: Test sequence compaction for sequential circuits with reset states. Asian Test Symposium 2000: 165-170
- [c47]Toshiyuki Maeda, Kozo Kinoshita: Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults. Asian Test Symposium 2000: 350-355
- [c46]Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita: A high-speed IDDQ sensor implementation. Asian Test Symposium 2000: 356-361
- [c45]Toshiyuki Maeda, Kozo Kinoshita: Precise test generation for resistive bridging faults of CMOS combinational circuits. ITC 2000: 510-519
- [c44]Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy: Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design 2000: 294-299
1990 – 1999
- 1999
- [c43]Arabi Keshk, Kozo Kinoshita, Yukiya Miura: Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. Asian Test Symposium 1999: 121-126
- [c42]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146
- [c41]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara: On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 147-152
- [c40]Arabi Keshk, Kozo Kinoshita, Yukiya Miura: IDDQ Current Dependency on Test Vectors and Bridging Resistance. Asian Test Symposium 1999: 158-163
- [c39]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara: On Test Generation with A Limited Number of Tests. Great Lakes Symposium on VLSI 1999: 12-15
- [c38]Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design 1999: 72-77
- 1998
- [c37]Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita: An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. Asian Test Symposium 1998: 58-63
- [c36]Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: Design for Diagnosability of CMOS Circuits. Asian Test Symposium 1998: 144-149
- [c35]Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita: Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA. Asian Test Symposium 1998: 272-277
- [c34]Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium 1998: 312-317
- [c33]Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita: A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium 1998: 327-
- [c32]Hiroyuki Yotsuyanagi, Kozo Kinoshita: Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. VTS 1998: 176-183
- 1997
- [j34]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita: Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electronic Testing 11(1): 81-92 (1997)
- [j33]Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita: IDDQ test vector selection for transistor short fault testing. Systems and Computers in Japan 28(5): 11-21 (1997)
- [j32]Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita: A diagnosis method for single logic design errors in gate-level combinational circuits. Systems and Computers in Japan 28(6): 30-39 (1997)
- [j31]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara: On invariant implication relations for removing partial circuits. Systems and Computers in Japan 28(7): 39-47 (1997)
- [c31]Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita: An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits. Asian Test Symposium 1997: 22-
- [c30]Hideyuki Ichihara, Kozo Kinoshita: On Acceleration of Logic Circuits Optimization Using Implication Relations. Asian Test Symposium 1997: 222-227
- [c29]
- [c28]Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy: A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design 1997: 82-87
- 1996
- [c27]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium 1996: 94-99
- [c26]Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita: A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits. FTCS 1996: 38-43
- 1995
- [j30]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partial scan design and test sequence generation based on reduced scan shift method. J. Electronic Testing 7(1-2): 115-124 (1995)
- [j29]Xiaoqing Wen, Kozo Kinoshita, Hideo Tamamoto, Hiroshi Yokoyama: Efficient Guided-Probe Fault Location Method for Sequential Circuits. IEICE Transactions 78-D(2): 122-129 (1995)
- [j28]Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita: Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis. IEICE Transactions 78-D(7): 811-816 (1995)
- [j27]Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita: Testing of k-FR Circuits under Highly Observable Condition. IEICE Transactions 78-D(7): 830-838 (1995)
- [j26]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita: Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. IEICE Transactions 78-D(7): 861-867 (1995)
- [j25]Noriyoshi Itazaki, Kozo Kinoshita, Hisao Naitoh: Test pattern generation for crosstalk faults considering the gate delay. Systems and Computers in Japan 26(7): 24-33 (1995)
- [j24]Hiroaki Ueda, Kozo Kinoshita: Evaluation of the maximum number of switching gates for CMOS circuits. Systems and Computers in Japan 26(14): 15-25 (1995)
- [j23]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy: Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1496-1504 (1995)
- [c25]Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita: Transistor leakage fault location with ZDDQ measurement. Asian Test Symposium 1995: 51-57
- [c24]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium 1995: 169-175
- [c23]Hiroaki Ueda, Kozo Kinoshita: Low power design and its testability. Asian Test Symposium 1995: 361-366
- [c22]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita: Synthesis for Testability by Sequential Redundancy Removal Using Retiming. FTCS 1995: 33-40
- [c21]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita: Resynthesis for sequential circuits designed with a specified initial state. VTS 1995: 152-157
- 1994
- [j22]Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita: An approach to the analysis and detection of crosstalk faults in digital VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 387-395 (1994)
- [c20]Yukiya Miura, Sachio Naito, Kozo Kinoshita: A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. ISCAS 1994: 77-80
- [c19]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC 1994: 624-630
- [c18]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy: On compacting test sets by addition and removal of test vectors. VTS 1994: 202-207
- 1993
- [j21]Yukiya Miura, Yasushi Wada, Kozo Kinoshita: Design of testing circuit and test generation for built-in current testing. Systems and Computers in Japan 24(5): 73-82 (1993)
- [j20]Seiji Kajihara, Kozo Kinoshita, Haruko Shiba: Removal of redundancy in combinational circuits under classification of undetectable faults. Systems and Computers in Japan 24(7): 31-40 (1993)
- [c17]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy: Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC 1993: 102-106
- [c16]Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita: Test generation for multiple faults based on parallel vector pair analysis. ICCAD 1993: 436-439
- 1992
- [j19]Xiaoqing Wen, Kozo Kinoshita: A Testable Design of Logic Circuits under Highly Observable Condition. IEEE Trans. Computers 41(5): 654-659 (1992)
- [c15]Seiji Kajihara, Haruko Shiba, Kozo Kinoshita: Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults. FTCS 1992: 263-270
- [c14]Xiaoqing Wen, Kozo Kinoshita: Testable Designs of Sequential Circuits Under Highly Observable Condition. ITC 1992: 632-641
- [c13]
- 1991
- [j18]Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita: Stuck-open faults test generation for cmos combinational circuits. Systems and Computers in Japan 22(9): 33-42 (1991)
- 1990
- [j17]Yuzo Takamatsu, Kozo Kinoshita: Extended selection of switching target faults in CONT algorithm for test generation. J. Electronic Testing 1(3): 183-189 (1990)
- [c12]Xiaoqing Wen, Kozo Kinoshita: Fault detection and diagnosis of k-UCP circuits under totally observable condition. FTCS 1990: 382-389
- [c11]Etienne Sicard, Kozo Kinoshita: On the evaluation of process-fault tolerance ability of CMOS integrated circuits. ITC 1990: 948-954
- [c10]Xiaoqing Wen, Kozo Kinoshita: A testable design of logic circuits under highly observable condition. ITC 1990: 955-963
1980 – 1989
- 1989
- [j16]Yuzo Takamatsu, Kozo Kinoshita: CONT: a concurrent test generation system. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 966-972 (1989)
- [j15]Noriyoshi Itazaki, Kozo Kinoshita: Test pattern generation for circuits with tri-state modules by Z-algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1327-1334 (1989)
- [c9]Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita: Row/column pattern sensitive fault detection in RAMs via built-in self-test. FTCS 1989: 36-43
- [c8]Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita: Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. ITC 1989: 327-336
- 1986
- [j14]Kozo Kinoshita, Kewal K. Saluja: Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. IEEE Trans. Computers 35(10): 862-870 (1986)
- [c7]Noriyoshi Itazaki, Kozo Kinoshita: Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm. ITC 1986: 105-112
- 1985
- [j13]C. Boswell, Kewal K. Saluja, Kozo Kinoshita: Design of Programmable Logic Arrays for Parallel Testing. Comput. Syst. Sci. Eng. 1(1): 5-16 (1985)
- [j12]Kewal K. Saluja, Kozo Kinoshita: Test Pattern Generation for API Faults in RAM. IEEE Trans. Computers 34(3): 284-287 (1985)
- [c6]Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita: A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. ITC 1985: 574-582
- 1984
- [c5]Kozo Kinoshita, Kewal K. Saluja: Built-in Testing of Memory Using On-chip Compact Testing Scheme. ITC 1984: 271-281
- 1983
- [j11]Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara: An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. IEEE Trans. Computers 32(11): 1038-1046 (1983)
- [c4]Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara: Test generation for scan design circuits with tri-state modules and bidirectional terminals. DAC 1983: 71-78
- [c3]Takuji Okamoto, Hiroyuki Shibata, Kozo Kinoshita: Design of High-Level Test Language for Digital LSI. ITC 1983: 508-513
- 1981
- [j10]Hideo Fujiwara, Kozo Kinoshita: A Design of Programmable Logic Arrays with Universal Tests. IEEE Trans. Computers 30(11): 823-828 (1981)
- [c2]Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita: An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2. DAC 1981: 59-65
1970 – 1979
- 1979
- [j9]Tsutomu Sasao, Kozo Kinoshita: On the Number of Fanout-Free Functions and Unate Cascade Functions. IEEE Trans. Computers 28(1): 66-72 (1979)
- [j8]Tsutomu Sasao, Kozo Kinoshita: Conservative Logic Elements and Their Universality. IEEE Trans. Computers 28(9): 682-685 (1979)
- 1978
- [j7]Tsutomu Sasao, Kozo Kinoshita: Cascade Realization of 3-Input 3-Output Conservative Logic Circuits. IEEE Trans. Computers 27(3): 214-221 (1978)
- [j6]Hideo Fujiwara, Kozo Kinoshita: Connection Assignments for Probabilistically Diagnosable Systems. IEEE Trans. Computers 27(3): 280-283 (1978)
- [j5]Hideo Fujiwara, Kozo Kinoshita: Some Existence Theorems for Probabilistically Diagnosable Systems. IEEE Trans. Computers 27(4): 379-384 (1978)
- [j4]Tsutomu Sasao, Kozo Kinoshita: Realization of Minimum Circuits with Two-Input Conservative Logic Elements. IEEE Trans. Computers 27(8): 749-752 (1978)
- [j3]Hideo Fujiwara, Kozo Kinoshita: On the Computational Complexity of System Diagnosis. IEEE Trans. Computers 27(10): 881-885 (1978)
- [c1]Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita: LORES - Logic Reorganization System. DAC 1978: 250-260
- 1976
- [j2]Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda: On Magnetic Bubble Logic Circuits. IEEE Trans. Computers 25(3): 247-253 (1976)
- 1975
- [j1]Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita: Easily Testable Sequential Machines with Extra Inputs. IEEE Trans. Computers 24(8): 821-826 (1975)
Coauthor Index
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last updated on 2013-05-16 22:09 CEST by the dblp team