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Michael Kishinevsky
2010 – today
- 2013
[c57]Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras, Raid Zuhair Ayoub: Dynamic voltage and frequency scaling for shared resources in multicore processor designs. DAC 2013: 114- 2012
- [j21]Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras: xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification. IEEE Design & Test of Computers 29(3): 80-88 (2012)
- [j20]Satrajit Chatterjee, Michael Kishinevsky: Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics. Formal Methods in System Design 40(2): 147-169 (2012)
- [c56]Daniel E. Holcomb, Alexander Gotmanov, Michael Kishinevsky, Sanjit A. Seshia: Compositional performance verification of NoC designs. MEMOCODE 2012: 1-10
- 2011
- [j19]Josep Carmona, Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky: A Scheduling Strategy for Synchronous Elastic Designs. Fundam. Inform. 108(1-2): 1-21 (2011)
- [j18]Marc Galceran Oms, Alexander Gotmanov, Jordi Cortadella, Michael Kishinevsky: Microarchitectural Transformations Using Elasticity. JETC 7(4): 18 (2011)
- [c55]Michael Kishinevsky, Alexander Gotmanov, Yuriy Viktorov: Challenges in Verifying Communication Fabrics. ITP 2011: 18-21
- [c54]Chen-Ling Chou, Radu Marculescu, Ümit Y. Ogras, Satrajit Chatterjee, Michael Kishinevsky, Dmitrii Loukianov: System interconnect design exploration for embedded MPSoCs. SLIP 2011: 1-8
- [c53]Alexander Gotmanov, Satrajit Chatterjee, Michael Kishinevsky: Verifying Deadlock-Freedom of Communication Fabrics. VMCAI 2011: 214-231
- [e1]Satnam Singh, Barbara Jobstmann, Michael Kishinevsky, Jens Brandt (Eds.): 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Cambridge, UK, 11-13 July, 2011. IEEE 2011, ISBN 978-1-4577-0117-7
- 2010
- [j17]Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky: On the Performance Evaluation of Multi-Guarded Marked Graphs with Single-Server Semantics. Discrete Event Dynamic Systems 20(3): 377-407 (2010)
- [j16]Josep Carmona, Jordi Cortadella, Michael Kishinevsky: New Region-Based Algorithms for Deriving Bounded Petri Nets. IEEE Trans. Computers 59(3): 371-384 (2010)
- [c52]Satrajit Chatterjee, Michael Kishinevsky: Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics. CAV 2010: 321-338
- [c51]Marc Galceran Oms, Jordi Cortadella, Dmitry Bufistov, Michael Kishinevsky: Automatic microarchitectural pipelining. DATE 2010: 961-964
- [c50]Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras: Quick formal modeling of communication fabrics to enable verification. HLDVT 2010: 42-49
- [c49]Marc Galceran Oms, Jordi Cortadella, Michael Kishinevsky: Symbolic performance analysis of elastic systems. ICCAD 2010: 778-785
- [c48]
- [c47]Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Michael Kishinevsky, Ümit Y. Ogras: Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. NOCS 2010: 125-134
2000 – 2009
- 2009
- [j15]David Bañeres, Jordi Cortadella, Michael Kishinevsky: A Recursive Paradigm to Solve Boolean Relations. IEEE Trans. Computers 58(4): 512-527 (2009)
- [j14]Josep Carmona, Jordi Cortadella, Michael Kishinevsky, Alexander Taubin: Elastic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(10): 1437-1455 (2009)
- [c46]Josep Carmona, Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky: Scheduling Synchronous Elastic Designs. ACSD 2009: 52-59
- [c45]Josep Carmona, Jordi Cortadella, Michael Kishinevsky: Genet: A Tool for the Synthesis and Mining of Petri Nets. ACSD 2009: 181-185
- [c44]Josep Carmona, Jordi Cortadella, Michael Kishinevsky: Divide-and-Conquer Strategies for Process Mining. BPM 2009: 327-343
- [c43]Dmitry Bufistov, Jordi Cortadella, Marc Galceran Oms, Jorge Júlvez, Michael Kishinevsky: Retiming and recycling for elastic systems with early evaluation. DAC 2009: 288-291
- [c42]Marc Galceran Oms, Jordi Cortadella, Michael Kishinevsky: Speculation in elastic systems. DAC 2009: 292-295
- [c41]David Bañeres, Jordi Cortadella, Michael Kishinevsky: Variable-latency design by function speculation. DATE 2009: 1704-1709
- [c40]David Bañeres, Jordi Cortadella, Michael Kishinevsky: Timing-driven N-way decomposition. ACM Great Lakes Symposium on VLSI 2009: 363-368
- 2008
- [j13]Jordi Cortadella, Michael Kishinevsky, Dmitry Bufistov, Josep Carmona, Jorge Júlvez: Elasticity and Petri Nets. T. Petri Nets and Other Models of Concurrency 1: 221-249 (2008)
- [c39]
- [c38]Josep Carmona, Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev: A Symbolic Algorithm for the Synthesis of Bounded Petri Nets. Petri Nets 2008: 92-111
- [c37]Josep Carmona, Jordi Cortadella, Michael Kishinevsky: A Region-Based Algorithm for Discovering Petri Nets from Event Logs. BPM 2008: 358-373
- [c36]Timothy Kam, Michael Kishinevsky, Jordi Cortadella, Marc Galceran Oms: Correct-by-construction microarchitectural pipelining. ICCAD 2008: 434-441
- [c35]Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang: A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. MEMOCODE 2008: 79-88
- 2007
- [j12]Michael Kishinevsky, Sandeep K. Shukla, Ken S. Stevens: Guest Editors' Introduction: GALS Design and Validation. IEEE Design & Test of Computers 24(5): 414-416 (2007)
- [c34]Jordi Cortadella, Michael Kishinevsky: Synchronous Elastic Circuits with Early Evaluation and Token Counterflow. DAC 2007: 416-419
- [c33]David Bañeres, Jordi Cortadella, Michael Kishinevsky: Layout-aware gate duplication and buffer insertion. DATE 2007: 1367-1372
- [c32]Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar: A general model for performance optimization of sequential systems. ICCAD 2007: 362-369
- 2006
- [c31]Michael Kishinevsky, Jordi Cortadella, Bill Grundmann, Sava Krstic, John O'Leary: Synchronous Elastic Circuits. CSR 2006: 3-5
- [c30]Jordi Cortadella, Michael Kishinevsky, Bill Grundmann: Synthesis of synchronous elastic architectures. DAC 2006: 657-662
- [c29]Sava Krstic, Jordi Cortadella, Michael Kishinevsky, John O'Leary: Synchronous Elastic Networks. FMCAD 2006: 19-30
- [c28]David Bañeres, Jordi Cortadella, Michael Kishinevsky: Dominator-based partitioning for delay optimization. ACM Great Lakes Symposium on VLSI 2006: 67-72
- [c27]Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky: Performance analysis of concurrent systems with early evaluation. ICCAD 2006: 448-455
- 2004
- [c26]David Bañeres, Jordi Cortadella, Michael Kishinevsky: A recursive paradigm to solve Boolean relations. DAC 2004: 416-421
- [c25]Laurent Arditi, Gérard Berry, Michael Kishinevsky: Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. FMCAD 2004: 128-143
- 2003
- [c24]Gérard Berry, Michael Kishinevsky, Satnam Singh: System Level Design and Verification Using a Synchronous Language. ICCAD 2003: 433-440
- 2002
- [j11]Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev: Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 109-130 (2002)
- [c23]Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem: Coordinated transformations for high-level synthesis of high performance microprocessor blocks. DAC 2002: 898-903
- 2000
- [c22]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev: Hardware and Petri Nets: Application to Asynchronous Circuit Design. ICATPN 2000: 1-15
1990 – 1999
- 1999
- [j10]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev: Decomposition and technology mapping of speed-independent circuits using Boolean relations. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1221-1236 (1999)
- [c21]Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev: Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems. DAC 1999: 110-115
- [c20]Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken: CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121
- [c19]Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens: Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. ICCAD 1999: 324-331
- 1998
- [j9]Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten: Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings. Formal Methods in System Design 12(1): 5-38 (1998)
- [j8]Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Jordi Cortadella, Luciano Lavagno: The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems. Journal of Circuits, Systems, and Computers 8(1): 67-118 (1998)
- [j7]Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev: Deriving Petri Nets for Finite Transition Systems. IEEE Trans. Computers 47(8): 859-882 (1998)
- [j6]Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev: Hazard-free implementation of speed-independent circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 749-771 (1998)
- [j5]Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin: Partial-scan delay fault testing of asynchronous circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1184-1199 (1998)
- [c18]Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev: Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. ACSD 1998: 152-163
- [c17]Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev: Asynchronous Interface Specification, Analysis and Synthesis. DAC 1998: 2-7
- [c16]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev: Lazy transition systems: application to timing optimization of asynchronous circuits. ICCAD 1998: 324-331
- 1997
- [j4]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev: A region-based theory for state assignment in speed-independent circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 793-812 (1997)
- [c15]Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev: Coupling Asynchrony and Interrupts: Place Chart Nets. ICATPN 1997: 328-347
- [c14]Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev: Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. ASYNC 1997: 240-253
- [c13]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev: Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. ED&TC 1997: 98-105
- [c12]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev: Decomposition and technology mapping of speed-independent circuits using Boolean relations. ICCAD 1997: 220-227
- [c11]Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin: Partial scan delay fault testing of asynchronous circuits. ICCAD 1997: 728-735
- 1996
- [j3]Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny: On the Models for Asynchronous Circuit Behaviour with OR Causality. Formal Methods in System Design 9(3): 189-233 (1996)
- [c10]Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten: A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings. Application and Theory of Petri Nets 1996: 346-365
- [c9]Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev: Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. DAC 1996: 63-66
- 1995
- [c8]Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev: On hazard-free implementation of speed-independent circuits. ASP-DAC 1995
- [c7]Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev: Synthesizing Petri nets from state-based models. ICCAD 1995: 164-171
- 1994
- [j2]Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky: Analysis and Identification of Speed-Independent Circuits on an Event Model. Formal Methods in System Design 4(1): 33-75 (1994)
- [j1]Michael Kishinevsky, Alex Kondratyev, Alexander Taubin: Specification and analysis of self-timed circuits. VLSI Signal Processing 7(1-2): 117-135 (1994)
- [c6]Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno: OR Causality: Modelling and Hardware Implementation. Application and Theory of Petri Nets 1994: 568-587
- [c5]Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev: Basic Gate Implementation of Speed-Independent Circuits. DAC 1994: 56-62
- [c4]Christian D. Nielsen, Michael Kishinevsky: Performance Analysis Based on Timing Simulation. DAC 1994: 70-76
- [c3]Luciano Lavagno, Antonio Lioy, Michael Kishinevsky: Testing redundant asynchronous circuits by variable phase splitting. EURO-DAC 1994: 328-333
- [c2]Alex Kondratyev, Alexander Taubin, Victor Varshavsky, Michael Kishinevsky, Edwige E. Pissaloux: Change Diagram : A behavioural model for very speed VLSI circuit/highly parallel systems. PDP 1994: 220-226
- 1992
- [c1]Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky: Analysis and Identification of Self-Timed Circuits. Designing Correct Circuits 1992: 275-287
Coauthor Index
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last updated on 2013-05-31 22:17 CEST by the dblp team