Uming Ko

Maurits Ortmanns, Timothy Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai: Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. J. Solid-State Circuits 48(1): 3-7 (2013)

Shekhar Borkar, Uming Ko, Ali Keshavarzi, Ali Keshavarzi, Eugenio Cantatore: EP3: Empowering the killer SoC applications of 2020. ISSCC 2013: 517

Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko: A 28 nm 0.6 V Low Power DSP for Mobile Applications. J. Solid-State Circuits 47(1): 35-46 (2012)

Uming Ko: Ultra-low power challenges for the next generation ASIC. ISLPED 2012: 365-366

Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko: A 28nm 0.6V low-power DSP for mobile applications. ISSCC 2011: 132-134

Gordon Gammie, Alice Wang, Hugh Mair, Rolf Lagerquist, Minh Chau, Philippe Royannez, Sumanth Gururajarao, Uming Ko: SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. Proceedings of the IEEE 98(2): 144-159 (2010)

Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko: A design platform for 90-nm leakage reduction techniques. DAC 2005: 549-550

Uming Ko, Poras T. Balsara: High-performance energy-efficient D-flip-flop circuits. IEEE Trans. VLSI Syst. 8(1): 94-98 (2000)

Uming Ko, Mike McMahan, Edgar Auslander: DSP for the Third Generation Wireless Communications. ICCD 1999: 516-520

Uming Ko, Poras T. Balsara, Ashwini K. Nanda: Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. VLSI Syst. 6(2): 299-308 (1998)

David Li, Andrew Pua, Pranjal Srivastava, Uming Ko: A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors. ICCD 1997: 726-731

June Jiang, Kan Lu, Uming Ko: High-performance, low-power design techniques for dynamic to static logic interface. ISLPED 1997: 12-17

Uming Ko, Andrew Pua, Anthony M. Hill, Pranjal Srivastava: Hybrid dual-threshold design techniques for high-performance processors with low-power features. ISLPED 1997: 307-311

Uming Ko, Anthony M. Hill, Poras T. Balsara: Design techniques for high performance, energy efficient control logic. ISLPED 1996: 97-100

Uming Ko, T. Balsara, Wai Lee: Low-power design techniques for high-performance CMOS adders. IEEE Trans. VLSI Syst. 3(2): 327-333 (1995)

Uming Ko, Poras T. Balsara: Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Trans. VLSI Syst. 3(3): 450-455 (1995)

Uming Ko, Poras T. Balsara, Ashwini K. Nanda: Energy optimization of multi-level processor cache architectures. ISLPD 1995: 45-49

Uming Ko, Dinesh G. Patel, Francois J. Henley: Contactless VLSI Laser Probing. ITC 1985: 930-937