Haruo Kobayashi

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi: Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. ASP-DAC 2013: 103-104

Kazuyuki Wakabayashi, Keisuke Kato, Takafumi Yamada, Osamu Kobayashi, Haruo Kobayashi, Fumitaka Abe, Kiichi Niitsu: Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator. J. Electronic Testing 28(5): 641-651 (2012)

Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi: CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation. J. Solid-State Circuits 47(11): 2701-2710 (2012)

Hong Gao, Lin Xing, Yasunori Kobori, Feng Zhao, Haruo Kobayashi, Shyunsuke Miwa, Atsushi Motozawa, Zachary Nosker, Kiichi Niitsu, Nobukazu Takai, Takahiro Odaguchi, Isao Nakanishi, Kenji Nemoto, Jun-ichi Matsuda: DC-DC converter with continuous-time feed-forward Sigma-Delta modulator control. APCCAS 2012: 65-68

Yasunori Kobori, Qiulin Zhu, Murong Li, Feng Zhao, Zachary Nosker, Shu Wu, Shaiful N. Mohyar, Masanori Onozawa, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu, Takahiro Odaguchi, Isao Nakanishi, Kenji Nemoto, Jun-ichi Matsuda, Asahi Kasei: Single inductor dual output DC-DC converter design with exclusive control. APCCAS 2012: 436-439

Guanglei Jin, Hao Chen, Chuan Gao, Yunpeng Zhang, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu, Khayrollah Hadidi: Digitally-controlled Gm-C bandpass filter. APCCAS 2012: 531-534

Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuta Arakawa, Daiki Hirabayashi, Yuji Yano, Tatsuhiro Gake, Nobukazu Takai, Takahiro J. Yamaguchi: Multi-bit sigma-delta TDC architecture with self-calibration. APCCAS 2012: 671-674

Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi: A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. ASP-DAC 2012: 553-554

Keisuke Kato, Fumitaka Abe, Kazuyuki Wakabayashi, Chuan Gao, Takafumi Yamada, Haruo Kobayashi, Osamu Kobayashi, Kiichi Niitsu: Two-Tone Signal Generation for Communication Application ADC Testing. ATS 2012: 179-184

Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira: A New Procedure for Measuring High-Accuracy Probability Density Functions. ATS 2012: 185-190

Kiichi Niitsu, Takahiro J. Yamaguchi, Masahiro Ishida, Haruo Kobayashi: Post-Silicon Jitter Measurements. ATS 2012: 258-263

Tomohiko Ogawa, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Satoshi Ito, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu: Design for Testability That Reduces Linearity Testing Time of SAR ADCs. IEICE Transactions 94-C(6): 1061-1064 (2011)

Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Satoshi Ito, Yohei Tan, Haruo Kobayashi: Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme. IEICE Transactions 94-C(7): 1233-1236 (2011)

Mitsuko Omori, Haruo Kobayashi, Tetsuya Tanioka, Miho Nishimura, Atsuko Yuasa, Yuko Yasuhara: An analysis of the stress of the elderly with dementia in day-care. NLPKE 2011: 439-442

Yuko Yasuhara, Kaori Harano, Eiji Fujikawa, Hiroyuki Fujinaga, Tetsuya Tanioka, Haruo Kobayashi, Glenn Pfaff, Usar Suragarn: Effectiveness of the integration of different types of quantitative and qualitative assessment indicators for the patients with ischemic heart disease who underwent percutaneous coronary intervention (PCI). NLPKE 2011: 454-458

Hao San, Haruo Kobayashi: Noise-Coupled Image Rejection Architecture of Complex Bandpass DeltaSigmaAD Modulator. IEICE Transactions 93-A(2): 390-394 (2010)

Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San, Tatsuji Matsuura, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori: SAR ADC Algorithm with Redundancy and Digital Error Correction. IEICE Transactions 93-A(2): 415-423 (2010)

Koji Asami, Hiroyuki Miyajima, Tsuyoshi Kurosawa, Takenori Tateiwa, Haruo Kobayashi: Timing skew compensation technique using digital filter with novel linear phase condition. ITC 2010: 334-342

Koji Asami, Takahide Suzuki, Hiroyuki Miyajima, Tetsuya Taura, Haruo Kobayashi: Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity. IEICE Transactions 92-A(2): 374-380 (2009)

Santhos A. Wibowo, Zhang Ting, Masashi Kono, Tetsuya Taura, Yasunori Kobori, Ken-ichi Onda, Haruo Kobayashi: Analysis of Coupled Inductors for Low-Ripple Fast-Response Buck Converter. IEICE Transactions 92-A(2): 451-455 (2009)

Hao San, Haruo Kobayashi: Cross-Noise-Coupled Architecture of Complex Bandpass DeltaSigmaAD Modulator. IEICE Transactions 92-A(4): 998-1003 (2009)

Ibuki Mori, Yoshihisa Yamada, Santhos A. Wibowo, Masashi Kono, Haruo Kobayashi, Yukihiro Fujimura, Nobukazu Takai, Toshio Sugiyama, Isao Fukai, Norihisa Onishi, Ichiro Takeda, Jun-ichi Matsuda: EMI Reduction by Spread-Spectrum Clocking in Digitally-Controlled DC-DC Converters. IEICE Transactions 92-A(4): 1004-1011 (2009)

Haruo Kobayashi: Foreword. IEICE Transactions 92-C(6): 745-746 (2009)

Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai, Masao Hotta: A Time-to-Digital Converter with small circuitry. ASP-DAC 2009: 109-110

Hao San, Hajime Konagaya, Feng Xu, Atsushi Motozawa, Haruo Kobayashi, Kazumasa Ando, Hiroshi Yoshida, Chieto Murayama, Kanichi Miyazawa: Novel Architecture of Feedforward Second-Order Multibit Delta-Sigma-AD Modulator. IEICE Transactions 91-A(4): 965-970 (2008)

Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada: A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Transactions 90-C(6): 1181-1188 (2007)

Takanori Komuro, Shingo Sobukawa, Hiroshi Sakayori, Masashi Kono, Haruo Kobayashi: Total Harmonic Distortion Measurement System of Electronic Devices up to 100 MHz With Remarkable Sensitivity. IEEE T. Instrumentation and Measurement 56(6): 2360-2368 (2007)

Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Masao Hotta: A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS. ASP-DAC 2007: 96-97

Takanori Komuro, Naoto Hayasaka, Haruo Kobayashi, Hiroshi Sakayori: A Practical Analog BIST Cooperated with an LSI Tester. IEICE Transactions 89-A(2): 465-468 (2006)

Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada: Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Transactions 89-A(4): 908-915 (2006)

Masafumi Uemori, Haruo Kobayashi, Tomonari Ichikawa, Atsushi Wada, Koichiro Mashiko, Toshiro Tsukada, Masao Hotta: High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC. IEICE Transactions 89-A(4): 916-923 (2006)

Jun Otsuki, Hao San, Haruo Kobayashi, Takanori Komuro, Yoshihisa Yamada, Aiyan Liu: Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths. IEICE Transactions 88-C(6): 1290-1294 (2005)

Takanori Komuro, Naoto Hayasaka, Haruo Kobayashi, Hiroshi Sakayori: A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI. ISCAS (5) 2005: 4281-4284

Hao San, Haruo Kobayashi, Shinya Kawakami, Nobuyuki Kuroiwa: An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators. VLSI Design 2004: 151-156

Haruo Kobayashi, Takashi Matsumoto, Tetsuya Yagi, Koji Tanaka: Light-adaptive architectures for regularization vision chips. Neural Networks 8(1): 87-101 (1995)

Haruo Kobayashi, Takashi Matsumoto, Jun Sanekata: Two-dimensional spatio-temporal dynamics of analog image processing neural networks. IEEE Trans. Neural Netw. Learning Syst. 6(5): 1148-1164 (1995)

Haruo Kobayashi, Hiroshi Sakayori, Tsutomu Tobari, Hiroyuki Matsuura: Error Correction Algorithm for Folding/Interpolation ADC. ISCAS 1995: 700-703

Haruo Kobayashi, Takashi Matsumoto, Tetsuya Yagi, Takuji Shimmi: Image processing regularization filters on layered architecture. Neural Networks 6(3): 327-350 (1993)