Cheng-Kok Koh

Anirudh Udupa, Ganesh Subbarayan, Cheng-Kok Koh: Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias. Microelectronics Reliability 53(1): 63-69 (2013)

Jiang Hu, Cheng-Kok Koh: Guest editorial: Special section on cross-domain physical optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 32(2): 173-174 (2013)

Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li: Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. ISPD 2013: 114-119

Rickard Ewetz, Cheng-Kok Koh: Local merges for effective redundancy in clock networks. ISPD 2013: 162-167

Cheng-Kok Koh, Cliff C. N. Sze (Eds.): International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013. ACM 2013, isbn 978-1-4503-1954-6

Stephen Cauley, Venkataramanan Balakrishnan, Gerhard Klimeck, Cheng-Kok Koh: A two-dimensional domain decomposition technique for the simulation of quantum-scale devices. J. Comput. Physics 231(4): 1293-1313 (2012)

Jiang Hu, Cheng-Kok Koh: Guest Editorial Special Section on the 2011 International Symposium on Physical Design. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 165-166 (2012)

Jongwon Lee, Duo Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Dan Jiao: A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 380-390 (2012)

Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Guoyong Shi, Grantham K. H. Pang, Ngai Wong: Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 532-545 (2012)

Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh: A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. ICCAD 2012: 713-719

Shuai Li, Cheng-Kok Koh: Mixed integer programming models for detailed placement. ISPD 2012: 87-94

Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan: A size scaling approach for mixed-size placement. ISPD 2012: 201-206

Jiang Hu, Cheng-Kok Koh (Eds.): International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012. ACM 2012, isbn 978-1-4503-1167-0

Stephen Cauley, Venkataramanan Balakrishnan, Y. Charlie Hu, Cheng-Kok Koh: A parallel branch-and-cut approach for detailed placement. ACM Trans. Design Autom. Electr. Syst. 16(2): 18 (2011)

Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao: Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC 2011: 633-638

Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh: Processor caches with multi-level spin-transfer torque ram cells. ISLPED 2011: 73-78

Tarun Mittal, Cheng-Kok Koh: Cross link insertion for improving tolerance to variations in clock network synthesis. ISPD 2011: 29-36

Shashank Bujimalla, Cheng-Kok Koh: Synthesis of low power clock trees for handling power-supply variations. ISPD 2011: 37-44

Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao: Optimal Double Via Insertion With On-Track Preference. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 318-323 (2010)

Stephen Cauley, Venkataramanan Balakrishnan, Cheng-Kok Koh: A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 29(4): 636-641 (2010)

Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy: Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. VLSI Syst. 18(11): 1621-1624 (2010)

Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K. H. Pang, Ngai Wong: PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation. ICCAD 2010: 800-807

Ao-Jan Su, Y. Charlie Hu, Aleksandar Kuzmanovic, Cheng-Kok Koh: How to Improve Your Google Ranking: Myths and Reality. Web Intelligence 2010: 50-57

Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li: Tolerating process variations in large, set-associative caches: The buddy cache. TACO 6(2) (2009)

Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Trans. VLSI Syst. 17(12): 1749-1752 (2009)

Wenwen Chai, Dan Jiao, Cheng-Kok Koh: A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. DAC 2009: 752-757

Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan: A study of routability estimation and clustering in placement. ICCAD 2009: 363-366

Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li: The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. ICCD 2009: 268-274

Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao: Fast and Optimal Redundant Via Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2197-2208 (2008)

Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan: Guiding global placement with wire density. ICCAD 2008: 212-217

Jitesh Jain, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan: A fast band matching technique for impedance extraction. ISCAS 2008: 2981-2984

Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao: Optimal post-routing redundant via insertion. ISPD 2008: 111-117

Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-Driven Placement and White Space Allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 858-871 (2007)

Ruibing Lu, Aiqun Cao, Cheng-Kok Koh: SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. IEEE Trans. VLSI Syst. 15(1): 69-79 (2007)

Ruilin Wang, Cheng-Kok Koh: A frequency-domain technique for statistical timing analysis of clock meshes. ICCAD 2007: 334-339

Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan: A fast band-matching technique for interconnect inductance modeling. ICCAD 2007: 568-571

Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li: VOSCH: Voltage scaled cache hierarchies. ICCD 2007: 496-503

Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh: Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED 2007: 195-200

Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical Timing Analysis Considering Spatial Correlations. ISQED 2007: 102-107

Hong Li, Jitesh Jain, Venkataramanan Balakrishnan, Cheng-Kok Koh: Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. ISQED 2007: 627-632

Chen Li, Cheng-Kok Koh: Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. ISQED 2007: 829-834

Ruibing Lu, Cheng-Kok Koh: Performance analysis of latency-insensitive systems. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 469-483 (2006)

Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, T.-S. Ng: Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2062-2075 (2006)

Aiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh: Postlayout optimization for synthesis of Domino circuits. ACM Trans. Design Autom. Electr. Syst. 11(4): 797-821 (2006)

Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh: SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163

Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan: SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. ASP-DAC 2006: 422-427

Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan: Adaptive admittance-based conductor meshing for interconnect analysis. ASP-DAC 2006: 509-514

Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh: Stable and compact inductance modeling of 3-D interconnect structures. ICCAD 2006: 1-6

Ameya R. Agnihotri, Satoshi Ono, Chen Li, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Patrick H. Madden: Mixed block placement via fractional cut recursive bisection. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 748-761 (2005)

Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005)

Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. VLSI Syst. 13(1): 75-85 (2005)

Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh: A Performance and Power Co-optimization Approach for Modern Processors. CIT 2005: 822-828

Aiqun Cao, Ruibing Lu, Cheng-Kok Koh: Post-layout logic duplication for synthesis of domino circuits with complex gates. ASP-DAC 2005: 260-265

Chen Li, Cheng-Kok Koh, Patrick H. Madden: Floorplan management: incremental placement for gate sizing and buffer insertion. ASP-DAC 2005: 349-354

Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong: Compact and stable modeling of partial inductance and reluctance matrices. ASP-DAC 2005: 507-510

Wai-Ching Douglas Lam, Cheng-Kok Koh: Process variation robust clock tree routing. ASP-DAC 2005: 606-611

Ruibing Lu, Aiqun Cao, Cheng-Kok Koh: Improving the scalability of SAMBA bus architecture. ASP-DAC 2005: 1164-1167

Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh: 3D module placement for congestion and power noise reduction. ACM Great Lakes Symposium on VLSI 2005: 458-461

Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical based link insertion for robust clock network design. ICCAD 2005: 588-591

Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Cascaded carry-select adder (C²SA): a new structure for low-power CSA design. ISLPED 2005: 115-118

Ruibing Lu, Cheng-Kok Koh: A high performance bus communication architecture through bus splitting. ASP-DAC 2004: 751-755

Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898

Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh: Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. DAC 2004: 369-374

Aiqun Cao, Cheng-Kok Koh: Post-layout logic optimization of domino circuits. DAC 2004: 820-825

Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan: Fast simulation of VLSI interconnects. ICCAD 2004: 93-98

Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-driven placement and white space allocation. ICCAD 2004: 394-401

Ateen Khatkhate, Chen Li, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden: Recursive bisection based mixed block placement. ISPD 2004: 84-89

Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: On-chip interconnect modeling by wire duplication. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1521-1532 (2003)

Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: A metric for analyzing effective on-chip inductive coupling. ASP-DAC 2003: 156-161

Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC 2003: 820-823

Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy: An adaptive window-based susceptance extraction and its efficient implementation. DAC 2003: 728-731

Ruibing Lu, Cheng-Kok Koh: Interconnect Planning with Local Area Constrained Retiming. DATE 2003: 10442-10447

Ruibing Lu, Cheng-Kok Koh: SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. ICCAD 2003: 8-12

Ruibing Lu, Cheng-Kok Koh: Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. ICCAD 2003: 227-231

Aiqun Cao, Cheng-Kok Koh: Non-Crossing OBDDs for Mapping to Regular Circuit Structures. ICCD 2003: 338-343

Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234

Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao: Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. ISQED 2003: 327-332

Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 81-92 (2002)

Chung-Wen Albert Tsao, Cheng-Kok Koh: UST/DME: a clock tree router for general skew constraints. ACM Trans. Design Autom. Electr. Syst. 7(3): 359-379 (2002)

Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh: A factorization-based framework for passivity-preserving model reduction of RLC systems. DAC 2002: 40-45

Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao: Flip-Flop and Repeater Insertion for Early Interconnect Planning. DATE 2002: 690-695

Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-935

Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: On-chip interconnect modeling by wire duplication. ICCAD 2002: 341-346

Guoan Zhong, Cheng-Kok Koh: Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. ICCD 2002: 428-433

Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234

Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao: Power Supply Noise Suppression via Clock Skew Scheduling. ISQED 2002: 355-360

Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh: Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. VLSI Design 2002: 311-316

Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. VLSI Design 2002: 489-

Probir Sarkar, Cheng-Kok Koh: Routability-driven repeater block planning for interconnect-centricfloorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 660-671 (2001)

Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001)

Jason Cong, Cheng-Kok Koh, Patrick H. Madden: Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1455-1463 (2001)

Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC 2001: 846-851

Probir Sarkar, Cheng-Kok Koh: Repeater block planning under simultaneous delay and transition time constraints. DATE 2001: 540-545

Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power trends and performance characterization of 3-dimensional integration. ISCAS (4) 2001: 414-417

Rui Wang, Kaushik Roy, Cheng-Kok Koh: Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) 2001: 886-889

Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy: Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270

Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Decoupling capacitance allocation for power supply noise suppression. ISPD 2001: 66-71

Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED 2001: 217-222

Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh (Eds.): Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001. ACM 2001, isbn 1-58113-351-0

Cheng-Kok Koh, Patrick H. Madden: Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. ACM Great Lakes Symposium on VLSI 2000: 47-52

Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD 2000: 208-213

Chung-Wen Albert Tsao, Cheng-Kok Koh: UST/DME: A Clock Tree Router for General Skew Constraints. ICCAD 2000: 400-405

Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD 2000: 406-411

Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD 2000: 487-492

Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD 2000: 65-72

Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar: Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246

Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh: Routability-driven repeater block planning for interconnect-centric floorplanning. ISPD 2000: 186-191

Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998)

Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. ICCAD 1997: 478-485

Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633

Jason Cong, Cheng-Kok Koh: Interconnect layout optimization under higher-order RLC model. ICCAD 1997: 713-720

Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden: Performance optimization of VLSI interconnect layout. Integration 21(1-2): 1-94 (1996)

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung: Simultaneous buffer and wire sizing for performance and power optimization. ISLPED 1996: 271-276

Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71

Jason Cong, Cheng-Kok Koh: Minimum-Cost Bounded-Skew Clock Routing. ISCAS 1995: 215-218

Jason Cong, Cheng-Kok Koh: Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. VLSI Syst. 2(4): 408-425 (1994)

Jason Cong, Cheng-Kok Koh: Simultaneous driver and wire sizing for performance and power optimization. ICCAD 1994: 206-212