Tetsushi Koide

Fengwei An, Tetsushi Koide, Hans Jürgen Mattausch: A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. IEICE Transactions 95-D(9): 2327-2338 (2012)

Hans Jürgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide: Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. J. Solid-State Circuits 47(6): 1448-1459 (2012)

Ali Ahmadi, Hans Jürgen Mattausch, Md. Anwarul Abedin, Mahmoud Saeidi, Tetsushi Koide: An associative memory-based learning model with an efficient hardware implementation in FPGA. Expert Syst. Appl. 38(4): 3499-3513 (2011)

Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Masaharu Tagami, Masakatsu Ishizaki: Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. IEICE Transactions 94-D(9): 1742-1754 (2011)

Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto: A Scalable Massively Parallel Processor for Real-Time Image Processing. J. Solid-State Circuits 46(10): 2363-2373 (2011)

Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide: Real-time hybrid learning and recognition system with software-hardware cooperation. ROBIO 2011: 2505-2510

Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika: Measurement-Based Ring Oscillator Variation Analysis. IEEE Design & Test of Computers 27(5): 6-13 (2010)

Akio Kawabata, Tetsushi Koide, Hans Jürgen Mattausch: Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. ICNC 2010: 15-19

Tetsushi Koide, R. Kimura, T. Sugahara, K. Okazaki, Hans Jürgen Mattausch: Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. ICNC 2010: 128-132

Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto: A scalable massively parallel processor for real-time image processing. ISSCC 2010: 334-335

Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Transactions 91-C(9): 1409-1418 (2008)

Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Transactions 90-D(1): 334-345 (2007)

Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch: Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Transactions 90-D(1): 346-354 (2007)

Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Shogo Sakakibara, Tetsushi Koide, Hans Jürgen Mattausch: Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Transactions 90-A(6): 1240-1243 (2007)

Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Transactions 90-D(8): 1312-1315 (2007)

Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka: 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Transactions 90-C(11): 2157-2160 (2007)

Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528

Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch: Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Transactions 89-D(3): 1299-1302 (2006)

Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto: A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Transactions 89-C(11): 1612-1619 (2006)

Takashi Morimoto, Hidekazu Adachi, K. Yamaoka, K. Awane, Tetsushi Koide, Hans Jürgen Mattausch: An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS 2006: 944-947

Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa: Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300

Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch: Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS 2006: 1309-1312

Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch: Application of Multi-ported CAM for Parallel Coding. APCCAS 2006: 1859-1862

K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch: Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC 2006: 176-181

K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, K. Awane, Tetsushi Koide, Hans Jürgen Mattausch: Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS 2006

Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara: Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Transactions 88-C(4): 622-629 (2005)

Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide: A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Transactions 88-C(6): 1332-1342 (2005)

Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide: Chip size and performance evaluations of shared cache for on-chip multiprocessor. Systems and Computers in Japan 36(9): 1-13 (2005)

Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch: A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC 2005: 13-14

Ali Ahmadi, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide: A parallel hardware design for parametric active contour models. AVSS 2005: 609-613

Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch: Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) 2005: 3215-3218

T. Saito, M. Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, K. Aoyama, Tetsushi Koide, Hans Jürgen Mattausch: Design of superscalar processor with multi-bank register file. ISCAS (4) 2005: 3507-3510

Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205

Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch: Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. IEICE Transactions 87-D(2): 500-503 (2004)

Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch: 350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. ASP-DAC 2004: 531-532

Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch: Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC 2004: 543-544

Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka: Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC 2004: 551-552

Tetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda: A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. ASP-DAC 2003: 591-592

Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide: A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Systems and Computers in Japan 33(12): 87-96 (2002)

Tetsushi Koide, S. Shinmori, H. Ishii: Topological optimization with a network reliability constraint. Discrete Applied Mathematics 115(1-3): 135-149 (2001)

Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide: Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Systems and Computers in Japan 32(1): 29-37 (2001)

Shin'ichi Wakabayashi, Tetsushi Koide, Nayoshi Toshine, Masataka Yamane, Hajime Ueno: Genetic algorithm accelerator GAA-II. ASP-DAC 2000: 9-10

Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi: Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC 2000: 99-104

Tetsushi Koide, Shin'ichi Wakabayashi: A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integration 27(1): 57-76 (1999)

Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta: An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC 1999: 37-40

Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide: Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC 1999: 181-184

Tetsushi Koide, Shin'ichi Wakabayashi: A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC 1998: 577-583

Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide: Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN 1998: 1028-1037

Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida: A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integration 24(1): 53-77 (1997)

Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru: Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1997: 133-140

Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A three-layer over-the-cell multi-channel router for a new cell model. Integration 21(3): 171-189 (1996)

Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: Pin assignment with global routing for VLSI building block layout. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1575-1583 (1996)

Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC 1995

Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru: A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1995

Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC 1995

Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida: An MCM Routing Algorithm Considering Crosstalk. ISCAS 1995: 211-214

Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida: A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS 1995: 1920-1923

Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A Floorplanning Method with Topological Constraint Manipulation. ISCAS 1994: 165-168

Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida: A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS 1994: 225-228

Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida: Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS 1993: 2059-2062