Zdenek Kotásek

Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka: Fault tolerant system design and SEU injection based testing. Microprocessors and Microsystems - Embedded Hardware Design 37(2): 155-173 (2013)

Zdenek Kotásek, Lukás Sekanina, Tomás Vojnar, Jan Bouda, Ivana Cerná: pecial CAI Section Devoted to MEMICS '11: Preface. Computing and Informatics 31(3): 481- (2012)

Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek: Test platform for fault tolerant systems design properties verification. DDECS 2012: 336-341

Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek: Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. DSD 2012: 250-257

Zdenek Kotásek, Jan Bouda, Ivana Cerná, Lukás Sekanina, Tomás Vojnar, David Antos (Eds.): Mathematical and Engineering Methods in Computer Science - 7th International Doctoral Workshop, MEMICS 2011, Lednice, Czech Republic, October 14-16, 2011, Revised Selected Papers. Lecture Notes in Computer Science 7119, Springer 2012, isbn 978-3-642-25928-9

Pavel Bartos, Zdenek Kotásek, Jan Dohnal: Decreasing test time by scan chain reorganization. DDECS 2011: 371-374

Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek: Advanced fault tolerant bus for multicore system implemented in FPGA. DDECS 2011: 397-398

Martin Straka, Jan Kastil, Zdenek Kotásek: SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems. DSD 2011: 223-230

Martin Straka, Jan Kastil, Zdenek Kotásek: Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. DDECS 2010: 173-176

Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel: Reduction of power dissipation through parallel optimization of test vector and scan register sequences. DDECS 2010: 364-369

Martin Straka, Jan Kastil, Zdenek Kotásek: Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. DSD 2010: 365-372

Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel: The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. DSD 2010: 644-651

Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel: The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. ICES 2010: 181-192

Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann (Eds.): 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010. IEEE 2010, isbn 978-1-4244-6612-2

Milan Ceska, Zdenek Kotásek, Mojmír Kretínský, Ludek Matyska, Tomás Vojnar: Preface. Electr. Notes Theor. Comput. Sci. 251: 1-3 (2009)

Martin Straka, Zdenek Kotásek: High Availability Fault Tolerant Architectures Implemented into FPGAs. DSD 2009: 108-115

Josef Strnadel, Tomas Pecenka, Zdenek Kotásek: Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics 27(6): 913-930 (2008)

Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda: Polymorphic Gates in Design and Test of Digital Circuits. IJUC 4(2): 125-142 (2008)

Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Testability analysis based on the identification of testable blocks with predefined properties. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 296-302 (2008)

Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek: Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Design Autom. Electr. Syst. 13(3) (2008)

Lukás Starecek, Lukás Sekanina, Zdenek Kotásek: Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS 2008: 255-268

Martin Straka, Zdenek Kotásek, Jan Winter: Digital Systems Architectures Based on On-line Checkers. DSD 2008: 81-87

Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Power Conscious RTL Test Scheduling. DSD 2008: 721-728

Martin Straka, Jiri Tobola, Zdenek Kotásek: Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. DFT 2007: 152-160

Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. DSD 2007: 611-618

Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka: Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD 2007: 676-679

Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek: Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS 2006: 186-193

Lukás Sekanina, Lukás Starecek, Zdenek Kotásek: Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS 2006: 85-86

Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina: FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS 2006: 285-289

Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina: Testability Estimation Based on Controllability and Observability Parameters. DSD 2006: 504-514

Josef Strnadel, Zdenek Kotásek: SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. ECBS 2006: 497-498

Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek (Eds.): Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006. IEEE Computer Society 2006, isbn 1-4244-0185-2

Josef Strnadel, Zdenek Kotásek: Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. DSD 2005: 420-427

Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel: Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware 2005: 51-58

Zdenek Kotásek, Daniel Mika, Josef Strnadel: Test scheduling for embedded systems. DSD 2003: 463-467

Josef Strnadel, Zdenek Kotásek: Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. DSD 2002: 166-173

J. Blatný, Zdenek Kotásek, Jan Hlavicka: RT Level Test Scheduling. Computers and Artificial Intelligence 16(1) (1997)

Zdenek Kotásek, F. Zboril: RT level testability analysis to reduce test application time. EUROMICRO 1997: 104-

J. Blatný, Zdenek Kotásek: I-Path Analysis. Computers and Artificial Intelligence 14(5) (1995)