Andrzej Krasniewski

Jakub Korczyc, Andrzej Krasniewski: Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching. DDECS 2012: 171-174

Grzegorz Borowik, Andrzej Krasniewski: Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs. EUROCAST (2) 2011: 327-334

Grzegorz Borowik, Andrzej Krasniewski: A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs. ICSEng 2011: 488-489

Andrzej Krasniewski: Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 303-312 (2008)

Andrzej Krasniewski: Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs. DDECS 2008: 74-79

Andrzej Krasniewski: Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs. DSD 2008: 250-255

Andrzej Krasniewski: Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs. DSD 2007: 579-586

Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino (Eds.): Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007. IEEE Computer Society 2007, isbn 1-4244-1161-0

Andrzej Krasniewski: Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs. DDECS 2006: 180-185

Andrzej Krasniewski: A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. IOLTS 2005: 197-198

Andrzej Krasniewski: Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs. DFT 2004: 487-495

Andrzej Krasniewski: Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. FPL 2004: 1067-1072

Andrzej Krasniewski: Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks. IOLTS 2004: 67-72

Andrzej Krasniewski: Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs. Journal of Systems Architecture 49(4-6): 283-296 (2003)

Andrzej Krasniewski: Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. FPL 2003: 828-838

Andrzej Krasniewski: Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption. IOLTS 2003: 168-

Andrzej Krasniewski: On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. FPL 2002: 596-606

Andrzej Krasniewski: Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. FPL 2002: 616-626

Andrzej Krasniewski: Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. DSD 2001: 310-317

Andrzej Krasniewski: Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing. IOLTW 2001: 37-

Andrzej Krasniewski: Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. FPL 2000: 675-684

Andrzej Krasniewski: Self-Testing of FPGA Delay Faults in the System Environment. IOLTW 2000: 40-

Pawel Tomaszewicz, Andrzej Krasniewski: Self-Testing of S-Compatible Test Units in User-Programmed FPGAs. EUROMICRO 1999: 1254-1259

Andrzej Krasniewski: Application-Dependent Testing of FPGA Delay Faults. EUROMICRO 1999: 1260-1267

Andrzej Krasniewski: Design of Dependable Hardware: What BIST is most Efficient? EDCC 1996: 233-245

Andrzej Krasniewski, Leszek B. Wronski: Coverage of Delay Faults: When 13% and 99% Mean the Same. EDCC 1994: 178-195

Andrzej Krasniewski, Leszek B. Wronski: Tests for path delay faults vs. tests for gate delay faults: how different they are. EURO-DAC 1994: 310-315

Slawomir Pilarski, Andrzej Krasniewski, Tiko Kameda: Estimating testing effectiveness of the circular self-test path technique. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1301-1316 (1992)

Xiaodong Xie, Alexander Albicki, Andrzej Krasniewski: Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion. ICCD 1992: 482-485

Andrzej Krasniewski, Slawomir Pilarski: High Quality Testing of Embedded RAMs Using Circular Self-Test Path. ITC 1992: 652-661

Andrzej Krasniewski: Logic Synthesis for Efficient Pseudoexhaustive Testability. DAC 1991: 66-72

Andrzej Krasniewski, Alexander Albicki: Random Testability of Redundant Circuits. ICCD 1991: 424-427

Andrzej Krasniewski: Can Redundancy Enhance Testability? ITC 1991: 483-491

Andrzej Krasniewski: Design for verification testability. EURO-DAC 1990: 644-648

Andrzej Krasniewski, Slawomir Pilarski: Circular self-test path: a low-cost BIST technique for VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 8(1): 46-55 (1989)

Andrzej Krasniewski, Slawomir Pilarski: Circular Self-Test Path: A Low-Cost BIST Technique. DAC 1987: 407-415

Andrzej Krasniewski, Alexander Albicki: Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. DAC 1985: 808-811

Andrzej Krasniewski, Alexander Albicki: Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. ITC 1985: 362-371

Andrzej Krasniewski: Fuzzy Automata as Adaptive Algorithms for Telephone Traffic Routing. ICC (1) 1984: 61-66