Sandip Kundu

Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel: A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. VLSI Syst. 21(2): 306-319 (2013)

Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu: Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. VLSI Design 2013: 80-85

Michael Buttrick, Sandip Kundu: On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs. J. Electronic Testing 28(1): 93-101 (2012)

Omer Khan, Sandip Kundu: Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime. IET Circuits, Devices & Systems 6(5): 355-365 (2012)

Aswin Sreedhar, Sandip Kundu, Israel Koren: On Reliability Trojan Injection and Detection. J. Low Power Electronics 8(5): 674-683 (2012)

Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu: A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays. IEEE Trans. Computers 61(7): 986-998 (2012)

Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu: A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1867-1880 (2012)

Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu: Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing. ACM Trans. Design Autom. Electr. Syst. 18(1): 5 (2012)

Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu: Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays. IEEE Trans. VLSI Syst. 20(3): 424-436 (2012)

Rance Rodrigues, Israel Koren, Sandip Kundu: A mechanism to verify cache coherence transactions in multicore systems. DFT 2012: 211-216

Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu: Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt. IPDPS Workshops 2012: 964-971

Sudarshan Srinivasan, Sandip Kundu: Functional test pattern generation for maximizing temperature in 3D IC chip stack. ISQED 2012: 109-116

Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu: On lithography aware metal-fill insertion. ISQED 2012: 200-207

Nishant Dhumane, Sandip Kundu: Critical area driven dummy fill insertion to improve manufacturing yield. ISQED 2012: 334-341

Kunal P. Ganeshpure, Sandip Kundu: Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes. ISVLSI 2012: 45-50

Kunal P. Ganeshpure, Sandip Kundu: A DFT Methodology for Repairing Embedded Memories of Large MPSoCs. ISVLSI 2012: 108-113

Arunkumar Vijayakumar, Raghavan Kumar, Sandip Kundu: On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors. ISVLSI 2012: 120-125

Raghavan Kumar, Vinay C. Patil, Sandip Kundu: On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators. ISVLSI 2012: 165-170

Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu: Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency. SBAC-PAD 2012: 59-66

Omer Khan, Sandip Kundu: Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. IEEE Trans. Dependable Sec. Comput. 8(5): 714-727 (2011)

Omer Khan, Sandip Kundu: Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. T. HiPEAC 4: 84-110 (2011)

Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan: Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. PACT 2011: 121-130

Rance Rodrigues, Israel Koren, Sandip Kundu: An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors. PACT 2011: 219

Rance Rodrigues, Sandip Kundu: An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors. Asian Test Symposium 2011: 161-166

Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich: Efficient BDD-based Fault Simulation in Presence of Unknown Values. Asian Test Symposium 2011: 383-388

Aswin Sreedhar, Sandip Kundu: On design of test structures for lithographic process corner identification. DATE 2011: 800-805

Sandip Kundu, Aswin Sreedhar: Modeling manufacturing process variation for design and test. DATE 2011: 1147-1152

Michael Buttrick, Sandip Kundu: On testing prebond dies with incomplete clock networks in a 3D IC using DLLs. DATE 2011: 1418-1423

Aswin Sreedhar, Sandip Kundu: Physically unclonable functions for embeded security based on lithographic variation. DATE 2011: 1632-1637

Rance Rodrigues, Israel Koren, Sandip Kundu: An Architecture to Enable Life Cycle Testing in CMPs. DFT 2011: 341-348

Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu: Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits. ACM Great Lakes Symposium on VLSI 2011: 265-270

Raghavan Kumar, Harikrishnan Kumarapillai Chandrikakutty, Sandip Kundu: On improving reliability of delay based Physically Unclonable Functions under temperature variations. HOST 2011: 142-147

Bharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu: Task model for on-chip communication infrastructure design for multicore systems. ICCD 2011: 360-365

Rance Rodrigues, Sandip Kundu: On graceful degradation of microprocessors in presence of faults via resource banking. IOLTS 2011: 61-66

Rance Rodrigues, Sandip Kundu: On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units. IOLTS 2011: 67-72

Aswin Sreedhar, Sandip Kundu: On discovery of "missing" physical design rules via diagnosis of soft-faults. ISQED 2011: 251-256

Rance Rodrigues, Sandip Kundu: Model based double patterning lithography (DPL) and simulated annealing (SA). ISQED 2011: 376-383

Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu: Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloads. ISQED 2011: 559-565

Michael Buttrick, Sandip Kundu: Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs. ISVLSI 2011: 194-199

Nishant Dhumane, Sudheendra K. Srivathsa, Sandip Kundu: Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability. ISVLSI 2011: 200-205

Raghavan Kumar, Vinay C. Patil, Sandip Kundu: Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain. ISVLSI 2011: 224-229

Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu: On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements. ISVLSI 2011: 248-253

Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu: Lithography aware critical area estimation and yield analysis. ITC 2011: 1-8

Alodeep Sanyal, Syed M. Alam, Sandip Kundu: BIST to Detect and Characterize Transient and Parametric Failures. IEEE Design & Test of Computers 27(5): 50-59 (2010)

Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey: Test pattern generation for droop faults. IET Computers & Digital Techniques 4(4): 274-284 (2010)

Omer Khan, Sandip Kundu: Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. IEEE Trans. Computers 59(5): 651-665 (2010)

Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu: An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects. IEEE Trans. Computers 59(7): 922-932 (2010)

Kunal P. Ganeshpure, Sandip Kundu: On ATPG for Multiple Aggressor Crosstalk Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 774-787 (2010)

Hyunbean Yi, Sandip Kundu, Sangwook Cho, Sungju Park: A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains. IEEE Trans. on Circuits and Systems 57-II(7): 561-565 (2010)

Hyunbean Yi, Sungju Park, Sandip Kundu: On-Chip Support for NoC-Based SoC Debugging. IEEE Trans. on Circuits and Systems 57-I(7): 1608-1617 (2010)

Rance Rodrigues, Sandip Kundu: A mask double patterning technique using litho simulation by wavelet transform. ACM Great Lakes Symposium on VLSI 2010: 103-106

Omer Khan, Sandip Kundu: A model to exploit power-performance efficiency in superscalar processors via structure resizing. ACM Great Lakes Symposium on VLSI 2010: 215-220

Shruti Vyas, Aswin Sreedhar, Sandip Kundu: TURBONFS: turbo nand flash search. ACM Great Lakes Symposium on VLSI 2010: 251-256

Omer Khan, Sandip Kundu: A self-adaptive scheduler for asymmetric multi-cores. ACM Great Lakes Symposium on VLSI 2010: 397-400

Anup Das, Rance Rodrigues, Israel Koren, Sandip Kundu: A study on performance benefits of core morphing in an asymmetric multicore processor. ICCD 2010: 17-22

Rance Rodrigues, Sandip Kundu, Omer Khan: Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. ITC 2010: 219-228

S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu: Modeling the impact of process variation on resistive bridge defects. ITC 2010: 295-304

Rance Rodrigues, Sandip Kundu: Optical Lithography Simulation with Focus Variation using Wavelet Transform. VLSI Design 2010: 387-392

Rishad Ahmed Shafik, Bashir M. Al-Hashimi, Sandip Kundu, Alireza Ejlali: Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip. J. Low Power Electronics 5(2): 145-156 (2009)

Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu: An Improved Soft-Error Rate Measurement Technique. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 596-600 (2009)

Omer Khan, Sandip Kundu: A self-adaptive system architecture to address transistor aging. DATE 2009: 81-86

Kelageri Nagaraj, Sandip Kundu: A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. DATE 2009: 292-295

Aswin Sreedhar, Sandip Kundu: On linewidth-based yield analysis for nanometer lithography. DATE 2009: 381-386

Abhisek Pan, Omer Khan, Sandip Kundu: Improving yield and reliability of chip multiprocessors. DATE 2009: 490-495

Omer Khan, Sandip Kundu: Hardware/software co-design architecture for thermal management of chip multiprocessors. DATE 2009: 952-957

Kunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker: Reducing temperature variability by routing heat pipes. ACM Great Lakes Symposium on VLSI 2009: 63-68

Aarti Choudhary, Sandip Kundu: A process variation tolerant self-compensating FinFET based sense amplifier design. ACM Great Lakes Symposium on VLSI 2009: 161-164

Kelageri Nagaraj, Sandip Kundu: Process variation mitigation via post silicon clock tuning. ACM Great Lakes Symposium on VLSI 2009: 227-232

Spandana Remarsu, Sandip Kundu: On process variation tolerant low cost thermal sensor design in 32nm CMOS technology. ACM Great Lakes Symposium on VLSI 2009: 487-492

Alodeep Sanyal, Abhisek Pan, Sandip Kundu: A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits. ACM Great Lakes Symposium on VLSI 2009: 529-534

Omer Khan, Sandip Kundu: Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. HiPEAC 2009: 293-307

Aswin Sreedhar, Sandip Kundu: Statistical timing analysis based on simulation of lithographic process. ICCD 2009: 29-34

Rance Rodrigues, Aswin Sreedhar, Sandip Kundu: Optical lithography simulation using wavelet transform. ICCD 2009: 427-432

Alodeep Sanyal, Abhisek Pan, Sandip Kundu: A study on impact of loading effect on capacitive crosstalk noise. ISQED 2009: 696-701

Aarti Choudhary, Sandip Kundu: A Process Variation Tolerant Self-Compensating Sense Amplifier Design. ISVLSI 2009: 263-267

Kunal P. Ganeshpure, Sandip Kundu: An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. VLSI Design 2009: 233-238

Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu: On Composite Leakage Current Maximization. J. Electronic Testing 24(4): 405-420 (2008)

Aswin Sreedhar, Sandip Kundu: Lithography Simulation Basics and a Study on Impact of Lithographic Process Window on Gate and Path Delays. J. Low Power Electronics 4(3): 392-401 (2008)

Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008)

Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu: On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. DATE 2008: 616-621

Sandip Kundu: The Guiding Light for Chip Testing. DDECS 2008: 1

Abhisek Pan, James W. Tschanz, Sandip Kundu: A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. DFT 2008: 343-351

Hyunbean Yi, Sandip Kundu: Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing. DFT 2008: 412-420

Omer Khan, Sandip Kundu: A framework for predictive dynamic temperature management of microprocessor systems. ICCAD 2008: 258-263

Aswin Sreedhar, Sandip Kundu: Modeling and analysis of non-rectangular transistors caused by lithographic distortions. ICCD 2008: 444-449

Alodeep Sanyal, Syed M. Alam, Sandip Kundu: A Built-In Self-Test Scheme for Soft Error Rate Characterization. IOLTS 2008: 65-70

Alodeep Sanyal, Sandip Kundu: A Built-in Test and Characterization Method for Circuit Marginality Related Failures. ISQED 2008: 838-843

Kelageri Nagaraj, Sandip Kundu: An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements. ITC 2008: 1-8

Aswin Sreedhar, Sandip Kundu: Statistical Yield Modeling for Sub-wavelength Lithography. ITC 2008: 1-8

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On Common-Mode Skewed-Load and Broadside Tests. VLSI Design 2008: 151-156

Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker: Power Droop Testing. IEEE Design & Test of Computers 24(3): 276-284 (2007)

Dimitris Gizopoulos, Robert C. Aitken, Sandip Kundu: Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems". IEEE Trans. VLSI Syst. 15(5): 493-494 (2007)

Ashesh Rastogi, Wei Chen, Sandip Kundu: On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. DAC 2007: 712-715

Kunal P. Ganeshpure, Sandip Kundu: Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. DATE 2007: 540-545

Aswin Sreedhar, Sandip Kundu: On modeling impact of sub-wavelength lithography on transistors. ICCD 2007: 84-90

Alodeep Sanyal, Sandip Kundu: On Derating Soft Error Probability Based on Strength Filtering. IOLTS 2007: 152-160

Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu: Accelerating Soft Error Rate Testing Through Pattern Selection. IOLTS 2007: 191-193

Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu: A Study on Impact of Leakage Current on Dynamic Power. ISCAS 2007: 1069-1072

Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu: On Accelerating Soft-Error Detection by Targeted Pattern Generation. ISQED 2007: 723-728

Kunal P. Ganeshpure, Sandip Kundu: On ATPG for multiple aggressor crosstalk faults in presence of gate delays. ITC 2007: 1-7

Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu: An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. VLSI Design 2007: 583-588

Sandip Kundu: TTTC technical forum honoring Sudhakar M. Reddy. IEEE Design & Test of Computers 23(2): 167 (2006)

Sandip Kundu: A design for failure analysis (DFFA) technique to ensure incorruptible signatures. DATE 2006: 309-310

Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu: A Pattern Generation Technique for Maximizing Power Supply Currents. ICCD 2006

Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker: Power Droop Testing. ICCD 2006

Sandip Kundu, Ilia Polian: An Improved Technique for Reducing False Alarms Due to Soft Errors. IOLTS 2006: 105-110

Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu: Test Pattern Generation for Power Supply Droop Faults. VLSI Design 2006: 343-348

Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti: On modeling crosstalk faults. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1909-1915 (2005)

Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Asian Test Symposium 2005: 266-271

Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker: Transient fault characterization in dynamic noisy environments. ITC 2005: 10

Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker: Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348

Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker: ITC 2003 Roundtable: Design for Manufacturability. IEEE Design & Test of Computers 21(2): 144-156 (2004)

Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy: Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers 53(1): 83-88 (2004)

Sandip Kundu: Pitfalls of hierarchical fault simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 312-314 (2004)

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1640-1649 (2004)

Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE 2004: 1078-1083

Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu: Static statistical timing analysis for latch-based pipeline designs. ICCAD 2004: 468-472

Sandip Kundu, T. M. Mak, Rajesh Galivanche: Trends in manufacturing test methods and their implications. ITC 2004: 679-687

Bill Grundmann, Rajesh Galivanche, Sandip Kundu: Circuit and Platform Design Challenges in Technologies beyond 90nm. DATE 2003: 10044-10049

Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti: On Modeling Cross-Talk Faults. DATE 2003: 10490-10495

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the Characterization of Hard-to-Detect Bridging Faults. DATE 2003: 11012-11019

Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC 2003: 1060-1068

Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy: On output response compression in the presence of unknown output values. DAC 2002: 255-258

Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche: Test Challenges in Nanometer Technologies. J. Electronic Testing 17(3-4): 209-218 (2001)

Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic: Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC 2001: 661-666

Sitaram Yadavalli, Sandip Kundu: On Fault-Simulation Through Embedded Memories On Large Industrial Designs. VLSI Design 2001: 117-121

Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu: Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC 2000: 587-592

Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu: On Detecting Bridges Causing Timing Failures. ICCD 1999: 400-406

Anirudh Devgan, Sandip Kundu: Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). ASP-DAC 1998: 345

Sandip Kundu: IDDQ Defect Detection in Deep Submicron CMOS ICs. Asian Test Symposium 1998: 150-152

Sandip Kundu: GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. ITC 1998: 372-381

Sandip Kundu, Uttam Ghoshal: Inductance analysis of on-chip interconnects [deep submicron CMOS]. ED&TC 1997: 252-255

Anirudh Devgan, Leon Stok, Sandip Kundu: Timing analysis and optimization: from devices to systems (tutorial). ICCAD 1997

Sandip Kundu, Egor S. Sogomonyan, Michael Gössel, Steffen Tarnick: Self-Checking Comparator with One Periodic Output. IEEE Trans. Computers 45(3): 379-380 (1996)

Sandip Kundu: On Construction of Non-systematic t-Symmetric Error Correcting/All Unidirectional Error Detecting Codes. IEICE Transactions 78-D(5): 596-599 (1995)

Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri: Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189-

Sandip Kundu: An incremental algorithm for identification of longest (shortest) paths. Integration 17(1): 25-31 (1994)

Sandip Kundu: An efficient technique for obtaining unate implementation of functions through input encoding. Integration 17(3): 265-270 (1994)

Leendert M. Huisman, Sandip Kundu: Highly Reliable Symmetric Networks. IEEE Trans. Parallel Distrib. Syst. 5(1): 94-97 (1994)

Sandip Kundu: Diagnosing scan chain faults. IEEE Trans. VLSI Syst. 2(4): 512-516 (1994)

Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther: Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294

Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain: Incremental synthesis. ICCAD 1994: 14-18

Sandip Kundu: Multifault Testable Circuits Based on Binary Parity Diagrams. ICCD 1994: 363-366

Ankan K. Pramanick, Sandip Kundu: Design of Scan-Based Path-Delay-Testable Sequential Circuits. ITC 1993: 962-971

Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy: A Small Test Generator for Large Designs. ITC 1992: 30-40

Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha: Design of robustly testable combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1036-1048 (1991)

Sandip Kundu, Sudhakar M. Reddy: Embedded Totally Self-Checking Checkers: A Practical Design. IEEE Design & Test of Computers 7(4): 5-12 (1990)

Sandip Kundu, Sudhakar M. Reddy: Robust tests for parity trees. J. Electronic Testing 1(3): 191-200 (1990)

Sandip Kundu, Sudhakar M. Reddy: On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. IEEE Trans. Computers 39(6): 752-761 (1990)

Sandip Kundu: Design of multioutput CMOS combinational logic circuits for robust testability. IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1222-1226 (1989)

Sandip Kundu, Sudhakar M. Reddy: On the design of robust testable CMOS combinational logic circuits. FTCS 1988: 220-225

Sandip Kundu, Sudhakar M. Reddy: Robust Tests for Parity Trees. ITC 1988: 680-687