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 | 2013 | |
|---|---|---|
| c55 |      | Bernard Schmidt, Carlos Villarraga, Jörg Bormann, Dominik Stoffel, Markus Wedler, Wolfgang Kunz: A computational model for SAT-based verification of hardware-dependent low-level embedded system software. ASP-DAC 2013: 711-716 |
| c54 |  | Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz, Jörg Bormann: A Hardware-Dependent Model for SAT-based Verification of Interrupt-Driven Low-level Embedded System Software. MBMV 2013: 49-60 |
| c53 | | Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Compositional Completeness over reactive Constraints. MBMV 2013: 83-96 |
| c52 | | Oliver Marx, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer: Proof Logging for Computer Algebra based SMT Solving. MBMV 2013: 255-265 |
| 2012 | ||
| c51 | | Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz: System verification of concurrent RTL modules by compositional path predicate abstraction. DAC 2012: 334-343 |
| c50 | | Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Formal plausibility checks for environment constraints. FDL 2012: 13-19 |
| 2011 | ||
| c49 | | Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Formal hardware/software co-verification by interval property checking with abstraction. DAC 2011: 510-515 |
| c48 | | Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel: STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra. DATE 2011: 155-160 |
| c47 | | Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel: STABLE: A new QF-BV SMT Solver for hard Verification Problems combining Boolean Reasoning with Computer Algebra. MBMV 2011: 51-60 |
| c46 | | Minh D. Nguyen, Markus Wedler, Bernard Schmidt, Dominik Stoffel, Wolfgang Kunz: Formal Hardware/Software Co-Verification by Interval Property Checking with Abstraction. MBMV 2011: 61-70 |
| c45 | | Christian Brehm, Norbert Wehn, Sacha Loitz, Wolfgang Kunz: Validation of channel decoding ASIPs a case study. International Symposium on Rapid System Prototyping 2011: 74-78 |
| 2010 | ||
| c44 | | Max Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Jörg Bormann, Wolfgang Kunz: Analyzing k-step induction to compute invariants for SAT-based property checking. DAC 2010: 176-181 |
| c43 | | Sacha Loitz, Markus Wedler, Dominik Stoffel, Christian Brehm, Norbert Wehn, Wolfgang Kunz: Complete Verification of Weakly Programmable IPs against Their Operational ISA Model. FDL 2010: 29-36 |
| c42 | | Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz: Path predicate abstraction by complete interval property checking. FMCAD 2010: 207-215 |
| c41 | | Max Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Analyzing k-step induction to compute invariants for SAT-based property checking. MBMV 2010: 87-96 |
| 2009 | ||
| c40 | | Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Jörg Bormann: A re-use methodology for formal SoC protocol compliance verification. FDL 2009: 1-6 |
| c39 | | Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz: A Re-Use Methodology for SoC Protocol Compliance Verification. MBMV 2009: 57-66 |
| 2008 | ||
| j11 | | Minh D. Nguyen, Max Thalmaier, Markus Wedler, Jörg Bormann, Dominik Stoffel, Wolfgang Kunz: Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2068-2082 (2008) |
| c38 | | Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber, Christian Jacobi, Matthias Pflanz: Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof. ASP-DAC 2008: 398-403 |
| c37 | | Oliver Wienand, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Gert-Martin Greuel: An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths. CAV 2008: 473-486 |
| c36 | | Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev: Modeling of Custom-Designed Arithmetic Components for ABL Normalization. FDL 2008: 124-129 |
| c35 | | Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev: Modeling of Custom-Designed Arithmetic Components for ABL Normalization. MBMV 2008: 51-60 |
| c34 | | Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz: Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking. SASP 2008: 48-54 |
| 2007 | ||
| j10 | | Markus Wedler, Dominik Stoffel, Raik Brinkmann, Wolfgang Kunz: A Normalization Method for Arithmetic Data-Path Verification. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1909-1922 (2007) |
| c33 | | Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Arithmetic Constraints in SAT-based Property Checking. MBMV 2007: 91-100 |
| c32 | | Martin Braun, Minh D. Nguyen, Hans Eveking, Martin Schickel, Wolfgang Kunz: Methoden zur Verifikation von Kommunikationsstrukturen. MBMV 2007: 223-232 |
| 2006 | ||
| c31 | | Alexander Jesser, Markus Wedler, Lars Hedrich, Wolfgang Kunz: A case study on applying bounded model checking to analog circuit verification. MBMV 2006: 106-113 |
| 2005 | ||
| c30 | | Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Normalization at the arithmetic bit level. DAC 2005: 457-462 |
| c29 | | Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz: Enhancing BMC-based Protocol Verification Using Transition-By-Transition FSM Traversal. GI Jahrestagung (1) 2005: 303-307 |
| c28 | | Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz: Transition-by-transition FSM traversal for reachability analysis in bounded model checking. ICCAD 2005: 1068-1075 |
| 2004 | ||
| j9 | | Dominik Stoffel, Wolfgang Kunz: Equivalence checking of arithmetic circuits on the arithmetic bit level. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 586-597 (2004) |
| j8 | | Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz: Structural FSM traversal. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 598-619 (2004) |
| c27 | | Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Exploiting state encoding for invariant generation in induction-based property checking. ASP-DAC 2004: 424-429 |
| c26 | | Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Arithmetic Reasoning in DPLL-Based SAT Solving. DATE 2004: 30-35 |
| c25 | | Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz: Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. ICCD 2004: 350-353 |
| c24 | | Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz: Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. MBMV 2004: 24-33 |
| e1 | | Dominik Stoffel, Wolfgang Kunz (Eds.): Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004. Shaker 2004 |
| 2003 | ||
| j7 | | Ingmar Neumann, Wolfgang Kunz: Layout driven retiming using the coupled edge timing model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 825-835 (2003) |
| c23 | | Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Using RTL Statespace Information and State Encoding for Induction Based Property Checking. DATE 2003: 11156-11157 |
| c22 | | Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Towards the impact of state encoding on induction-based property checking. MBMV 2003: 199-208 |
| 2002 | ||
| c21 | | Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas P. P. P. van Ginneken: Improving Placement under the Constant Delay Model. DATE 2002: 677-682 |
| c20 | | Armin Biere, Wolfgang Kunz: SAT and ATPG: Boolean engines for formal hardware verification. ICCAD 2002: 782-785 |
| c19 | | Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz: Accelerating Retiming Under the Coupled-Edge Timing Model. ISVLSI 2002: 135-140 |
| c18 | | Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation. ISVLSI 2002: 151-158 |
| c17 | | Kolja Sulimma, Ingmar Neumann, Lukas P. P. P. van Ginneken, Wolfgang Kunz: Improving Placement under the Constant Delay Model. MBMV 2002: 67-75 |
| 2001 | ||
| j6 | | Wolfgang Kunz, Dominik Stoffel: Äquivalenzvergleich mit strukturellen Methoden (Equivalence Checking using Structural Methods). it+ti - Informationstechnik und Technische Informatik 43(1): 8-15 (2001) |
| c16 | | Ingmar Neumann, Wolfgang Kunz: Placement Driven Retiming with a Coupled Edge Timing Model. ICCAD 2001: 95-102 |
| c15 | | Dominik Stoffel, Wolfgang Kunz: Verification of Integer Multipliers on the Arithmetic Bit Level. ICCAD 2001: 183-189 |
| c14 | | Ingmar Neumann, Wolfgang Kunz: Tight coupling of timing-driven placement and retiming. ISCAS (5) 2001: 351-354 |
| c13 | | Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz: Cycle time optimization by timing driven placement with simultaneous netlist transformations. ISCAS (5) 2001: 359-362 |
| c12 | | Kolja Sulimma, Wolfgang Kunz: An exact algorithm for solving difficult detailed routing problems. ISPD 2001: 198-203 |
| c11 | | Ingmar Neumann, Wolfgang Kunz: Performance Optimization during Placement by Retiming. MBMV (2) 2001: 19-28 |
| 1999 | ||
| c10 | | Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz: Accelerating Boolean Implications with FPGAs. FPL 1999: 532-537 |
| c9 | | Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz: Cell replication and redundancy elimination during placement for cycle time optimization. ICCAD 1999: 25-30 |
| 1998 | ||
| j5 | | Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz: LOT: Logic Optimization with Testability. New transformations for logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 386-399 (1998) |
| 1997 | ||
| j4 | | Wolfgang Kunz, Dominik Stoffel, Premachandran R. Menon: Logic optimization and equivalence checking by implication analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 266-281 (1997) |
| c8 | | Dominik Stoffel, Wolfgang Kunz, Stefan Gerber: AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks. ASP-DAC 1997: 529-538 |
| c7 | | Dominik Stoffel, Wolfgang Kunz: Record & play: a structural fixed point iteration for sequential circuit verification. ICCAD 1997: 394-399 |
| 1996 | ||
| j3 | | Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy: A novel framework for logic verification in a synthesis environment. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 20-32 (1996) |
| c6 | | Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz: Gate-level synthesis for low-power using new transformations. ISLPED 1996: 297-300 |
| 1995 | ||
| c5 | | Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan: Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. DAC 1995: 414-419 |
| c4 | | Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz: LOT: logic optimization with testability-new transformations using recursive learning. ICCAD 1995: 318-325 |
| 1994 | ||
| j2 | | Wolfgang Kunz, Dhiraj K. Pradhan: Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1143-1158 (1994) |
| c3 | | Wolfgang Kunz, Premachandran R. Menon: Multi-level logic optimization by implication analysis. ICCAD 1994: 6-13 |
| 1993 | ||
| j1 | | Wolfgang Kunz, Dhiraj K. Pradhan: Accelerated dynamic learning for test pattern generation in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 684-694 (1993) |
| c2 | | Wolfgang Kunz: HANNIBAL: an efficient tool for logic verification based on recursive learning. ICCAD 1993: 538-543 |
| 1992 | ||
| c1 | | Wolfgang Kunz, Dhiraj K. Pradhan: Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. ITC 1992: 816-825 |
Colors in the list of coauthors
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