Fadi J. Kurdahi

Le-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Houman Homayoun: Heterogeneous memory management for 3D-DRAM and external DRAM with QoS. ASP-DAC 2013: 663-668

Amin Khajeh, Minyoung Kim, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi: Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications. ACM Trans. Embedded Comput. Syst. 11(S1): 15 (2012)

Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling. IEEE Trans. VLSI Syst. 20(4): 630-642 (2012)

Muhammed S. Khairy, Chung-An Shen, Ahmed M. Eltawil, Fadi J. Kurdahi: Error resilient MIMO detector for memory-dominated wireless communication systems. GLOBECOM 2012: 3566-3571

Samy Zaynoun, Muhammed S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi, Amin Khajeh: Fast error aware model for arithmetic and logic circuits. ICCD 2012: 322-328

Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi: History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring. ISQED 2012: 498-505

Kiarash Amiri, Shih-Hsien Yang, Fadi J. Kurdahi, Magda El Zarki, Aditi Majumder: Collaborative video playback on a federation of tiled mobile projectors enabled by visual feedback. MMSys 2012: 113-118

Ihsen Alouani, Smaïl Niar, Fadi J. Kurdahi, Mohamed Abid: Parity-based mono-Copy Cache for low power consumption and high reliability. RSP 2012: 44-48

Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt: A Multi-Granularity Power Modeling Methodology for Embedded Processors. IEEE Trans. VLSI Syst. 19(4): 668-681 (2011)

Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation. IEEE Trans. VLSI Syst. 19(9): 1597-1609 (2011)

Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi: Embedded Memories Fault-Tolerant Pre- and Post-Silicon Optimization. IEEE Trans. VLSI Syst. 19(10): 1916-1921 (2011)

Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed M. Eltawil, Fadi J. Kurdahi: Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations. CODES+ISSS 2011: 257-266

Amr M. A. Hussien, Muhammed S. Khairy, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi: A Class of Low Power Error Compensation Iterative Decoders. GLOBECOM 2011: 1-6

Amir Hossein Gholamipour, Ali Gorcin, Hasari Celebi, B. Ugur Töreyin, Mazen A. R. Saghir, Fadi J. Kurdahi, Ahmed M. Eltawil: Reconfigurable filter implementation of a matched-filter based spectrum sensor for Cognitive Radio systems. ISCAS 2011: 2457-2460

Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt: CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis. IEEE Trans. VLSI Syst. 18(2): 209-221 (2010)

Fadi J. Kurdahi, Ahmed M. Eltawil, Kang Yi, Stanley Cheng, Amin Khajeh Djahromi: Low-Power Multimedia System Design by Aggressive Voltage Scaling. IEEE Trans. VLSI Syst. 18(5): 852-856 (2010)

Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt: Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications. IEEE Trans. VLSI Syst. 18(9): 1376-1380 (2010)

Arup Chakraborty, Houman Homayoun, Amin Khajeh, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi: E < MC2: less energy through multi-copy cache. CASES 2010: 237-246

Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt: Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. Conf. Computing Frontiers 2010: 297-308

Kiarash Amiri, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi: Process variation aware transcoding for low power H.264 decoding. ESTImedia 2010: 90-96

Amir Hossein Gholamipour, Fadi J. Kurdahi, Ahmed M. Eltawil, Mazen A. R. Saghir: Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters. FPL 2010: 175-178

Amin Khajeh, Kiarash Amiri, Muhammed S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi: A Unified Hardware and Channel Noise Model for Communication Systems. GLOBECOM 2010: 1-5

Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt: RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. HiPEAC 2010: 216-231

Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi: Effect of body biasing on embedded SRAM failure. ISCAS 2010: 2350-2353

Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi: Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. ISQED 2010: 499-507

Fadi J. Kurdahi: Designing working systems with imperfect chips. SBCCI 2010: 127

Fadi J. Kurdahi, Jarmo Takala (Eds.): Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010), Samos, Greece, July 19-22, 2010. IEEE 2010, isbn 978-1-4244-7937-5

Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi: System-level PVT variation-aware power exploration of on-chip communication architectures. ACM Trans. Design Autom. Electr. Syst. 14(2) (2009)

Mohammad A. Makhzan, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi: A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment. IEEE Trans. VLSI Syst. 17(6): 827-837 (2009)

Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi: Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. ASP-DAC 2009: 25-30

Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache). CASES 2009: 251-260

Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir: TRAM: A tool for Temperature and Reliability Aware Memory Design. DATE 2009: 340-345

Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling. DATE 2009: 911-916

Amir Hossein Gholamipour, Hamid Eslami, Ahmed M. Eltawil, Fadi J. Kurdahi: Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems. FCCM 2009: 71-78

Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi: Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. VLSI Design 2009: 499-504

Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt: Methodology for multi-granularity embedded processor power model generation for an ESL design flow. CODES+ISSS 2008: 255-260

Amin Khajeh Djahromi, Minyoung Kim, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi: Cross-layer co-exploration of exploiting error resilience for video over wireless applications. ESTImedia 2008: 13-18

Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. ISQED 2008: 470-475

Mohammad A. Makhzan, Ahmed M. Eltawil, Fadi J. Kurdahi: Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices. ICSAMOS 2008: 124-131

Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif: Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. VLSI Design 2008: 14-15

Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt: Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. VLSI Design 2008: 363-370

Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi: PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. VLSI Design 2008: 421-427

Chunhui Zhang, Fadi J. Kurdahi: Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications. International Journal of Parallel Programming 35(1): 63-98 (2007)

Chunhui Zhang, Yun Long, Fadi J. Kurdahi: A hierarchical pipelining architecture and FPGA implementation for lifting-based 2-D DWT. J. Real-Time Image Processing 2(4): 281-291 (2007)

Chunhui Zhang, Yun Long, Fadi J. Kurdahi: A scalable embedded JPEG 2000 architecture. Journal of Systems Architecture 53(8): 524-538 (2007)

Kang Yi, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil: An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories. Asia-Pacific Computer Systems Architecture Conference 2007: 102-113

Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ASP-DAC 2007: 274-279

Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Djahromi, Mohammad A. Makhzan, Stanley Cheng: Error-Aware Design. DSD 2007: 8-15

Amin Khajeh, Shih-Yang Cheng, Ahmed M. Eltawil, Fadi J. Kurdahi: Power Management for Cognitive Radio Platforms. GLOBECOM 2007: 4066-4070

Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi: Limits on voltage scaling for caches utilizing fault tolerant techniques. ICCD 2007: 488-495

Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt: System level power estimation methodology with H.264 decoder prediction IP case study. ICCD 2007: 601-608

Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj: Cross Layer Error Exploitation for Aggressive Voltage Scaling. ISQED 2007: 192-197

Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. VLSI Design 2007: 559-564

Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi: Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design. VTC Spring 2007: 2600-2604

Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi: Compile-time area estimation for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 11(1): 104-122 (2006)

Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil: Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs. Asia-Pacific Computer Systems Architecture Conference 2006: 295-308

Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Floorplan driven leakage power aware IP-based SoC design space exploration. CODES+ISSS 2006: 118-123

Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt: System-level power-performance trade-offs in bus matrix communication architecture synthesis. CODES+ISSS 2006: 300-305

Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif: System-Level SRAM Yield Enhancement. ISQED 2006: 179-184

Chunhui Zhang, Fadi J. Kurdahi: On combining iteration space tiling with data space tiling for scratch-pad memory systems. ASP-DAC 2005: 973-976

Chunhui Zhang, Yun Long, Fadi J. Kurdahi: A Scalable Embedded JPEG2000 Architecture. SAMOS 2005: 334-343

Yun Long, Chunhui Zhang, Fadi J. Kurdahi: A high-performance parallel mode EBCOT encoder architecture design for JPEG2000. SoCC 2004: 213-216

Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes: Automatic compilation to a coarse-grained reconfigurable system-opn-chip. ACM Trans. Embedded Comput. Syst. 2(4): 560-589 (2003)

Behzad Mohebbi, Eliseu Chavez Filho, Rafael Maestre, Mark Davies, Fadi J. Kurdahi: A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core. CODES+ISSS 2003: 103-108

Fadi J. Kurdahi: Guest editorial special issue on system synthesis. IEEE Trans. VLSI Syst. 10(4): 377-378 (2002)

Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Román Hermida, Nader Bagherzadeh, Fadi J. Kurdahi: A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. DATE 2002: 547-552

Hooman Parizi, Afshin Niktash, Nader Bagherzadeh, Fadi J. Kurdahi: MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note). Euro-Par 2002: 844-848

Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi: Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. FCCM 2002: 239-

Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh: Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing. Journal of Systems Architecture 47(3-4): 277-292 (2001)

Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh: A framework for reconfigurable computing: task scheduling and context management. IEEE Trans. VLSI Syst. 9(6): 858-873 (2001)

Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm: A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. CASES 2001: 116-125

Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi: A constraint-based application model and scheduling techniques for power-aware systems. CODES 2001: 153-158

Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi: Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. DAC 2001: 840-845

Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh: A data scheduler for multi-context reconfigurable architectures. ISSS 2001: 177-182

Fadi J. Kurdahi, Nader Bagherzadeh, Peter Athanas, Jose L. Muñoz: Guest Editors' Introduction: Configurable Computing. IEEE Design & Test of Computers 17(1): 17-19 (2000)

Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho: MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. IEEE Trans. Computers 49(5): 465-481 (2000)

Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves: Design and Implementation of the MorphoSys Reconfigurable Computing Processor. VLSI Signal Processing 24(2-3): 147-164 (2000)

Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh: MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. DAC 2000: 573-578

Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh: Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. FCCM 2000: 297-298

Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh: Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. ICCD 2000: 575-576

Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Nader Bagherzadeh, Hartej Singh: Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. ISSS 2000: 107-114

Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm: High-level synthesis of recoverable VLSI microarchitectures. IEEE Trans. VLSI Syst. 7(4): 401-410 (1999)

Min Xu, Fadi J. Kurdahi: Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs. IEEE Trans. VLSI Syst. 7(4): 411-418 (1999)

Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández: Kernel Scheduling in Reconfigurable Computing. DATE 1999: 90-96

Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves: The MorphoSys Dynamically Reconfigurable System-on-Chip. Evolvable Hardware 1999: 152-160

Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho: The MorphoSys Parallel Reconfigurable System. Euro-Par 1999: 727-734

Guangming Lu, Ming-Hau Lee, Hartej Singh, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho: MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application. IPPS/SPDP Workshops 1999: 661-669

Min Xu, Fadi J. Kurdahi: Layout-Driven High Level Synthesis for FPGA Based Architectures. DATE 1998: 446-450

Dirk Stroobandt, Fadi J. Kurdahi: On the Characterization of Multi-Point Nets in Electronic Designs. Great Lakes Symposium on VLSI 1998: 344-

Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt: A unified lower bound estimation technique for high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 458-472 (1997)

Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm: Optimal algorithms for recovery point insertion in recoverable microarchitectures. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 945-955 (1997)

Min Xu, Fadi J. Kurdahi: Layout-driven RTL binding techniques for high-level synthesis using accurate estimators. ACM Trans. Design Autom. Electr. Syst. 2(4): 312-343 (1997)

Min Xu, Fadi J. Kurdahi: ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications. ASP-DAC 1997: 435-440

Min Xu, Fadi J. Kurdahi: RTL synthesis with physical and controller information. ED&TC 1997: 299-303

Min Xu, Fadi J. Kurdahi: Layout-Driven RTL Binding Techniques for High-Level Synthesis. ISSS 1996: 33-38

A. Sriram, Fadi J. Kurdahi: Behavioral Modeling of an ATM Switch using SpecCharts. VLSI Design 1996: 19-22

Seong Yong Ohm, Fadi J. Kurdahi, Chu Shik Jhon: An Optimal Scheduling Approach Using Lower Bound in High-Level Synthesis. IEICE Transactions 78-D(3): 231-236 (1995)

Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm: Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures. FTCS 1995: 50-59

Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu: A comprehensive estimation technique for high-level synthesis. ISSS 1995: 122-127

Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran: On the intrinsic Rent parameter and spectra-based partitioning methodologies. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 27-37 (1994)

Champaka Ramachandran, Fadi J. Kurdahi: Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1450-1460 (1994)

Champaka Ramachandran, Fadi J. Kurdahi: Incorporating the Controller Effects During Register Transfer Level Synthesis. EDAC-ETC-EUROASIC 1994: 308-313

Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt: Comprehensive lower bound estimation from behavioral descriptions. ICCAD 1994: 182-187

Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi: An Empirical Study on the Effects of Physical Design in High-Level Synthesis. VLSI Design 1994: 11-16

D. Sreenivasa Rao, Fadi J. Kurdahi: On clustering for maximal regularity extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1198-1208 (1993)

Fadi J. Kurdahi, Champaka Ramachandran: Evaluating layout area tradeoffs for high level applications. IEEE Trans. VLSI Syst. 1(1): 46-55 (1993)

D. Sreenivasa Rao, Fadi J. Kurdahi: Hierarchical design space exploration for a class of digital systems. IEEE Trans. VLSI Syst. 1(3): 282-295 (1993)

D. Sreenivasa Rao, Fadi J. Kurdahi: Partitioning by Regularity Extraction. DAC 1992: 235-238

Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul: Accurate layout area and delay modeling for system level design. ICCAD 1992: 355-361

James J. Kim, Fadi J. Kurdahi, Nohbyung Park: Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths. ICCAD 1991: 30-33

Fadi J. Kurdahi, Alice C. Parker: Techniques for area estimation of VLSI layouts. IEEE Trans. on CAD of Integrated Circuits and Systems 8(1): 81-92 (1989)

Fadi J. Kurdahi, Alice C. Parker: REAL: a program for REgister ALlocation. DAC 1987: 210-215

Fadi J. Kurdahi, Alice C. Parker: PLEST: a program for area estimation of VLSI integrated circuits. DAC 1986: 467-473

Alice C. Parker, Fadi J. Kurdahi, Mitch J. Mlinar: A general methodology for synthesis and verification of register-transfer designs. DAC 1984: 329-335