Atsushi Kurokawa

Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue: Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies. Journal of Circuits, Systems, and Computers 21(6) (2012)

Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue: A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect. IEICE Transactions 94-A(5): 1201-1209 (2011)

Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto: Impact of Self-Heating in Wire Interconnection on Timing. IEICE Transactions 93-C(3): 388-392 (2010)

Kazuyuki Ooya, Yuji Takashima, Atsushi Kurokawa: Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage. IEICE Transactions 93-A(9): 1585-1593 (2010)

Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 250-260 (2010)

Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato: Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Transactions 92-A(4): 990-997 (2009)

Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue: Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model. IEICE Transactions 92-A(10): 2531-2539 (2009)

Yuji Takashima, Kazuyuki Ooya, Atsushi Kurokawa: Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability. IEICE Transactions 92-A(12): 2962-2970 (2009)

Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto: An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Transactions 92-A(12): 3016-3023 (2009)

Atsushi Kurokawa, Hiroshi Fujita, Tetsuya Ibe: Prevention in a Chip of EMI Noise Caused by X'tal Oscillator. IEICE Transactions 91-A(4): 1077-1083 (2008)

Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ASP-DAC 2007: 565-570

Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue: Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. IEICE Transactions 89-A(4): 840-846 (2006)

Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda: Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Transactions 89-A(4): 847-855 (2006)

Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue: Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Transactions 89-A(4): 856-864 (2006)

Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto: Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Transactions 89-A(12): 3666-3670 (2006)

Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye: A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. ICCAD 2006: 47-53

Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao: A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. IEICE Transactions 88-A(10): 2562-2569 (2005)

Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda: A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Transactions 88-A(11): 3180-3187 (2005)

Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue: Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Transactions 88-A(12): 3367-3374 (2005)

Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao: Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm. IEICE Transactions 88-A(12): 3412-3420 (2005)

Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions 88-A(12): 3453-3462 (2005)

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Transactions 88-A(12): 3471-3478 (2005)

Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue: Effective capacitance for gate delay with RC loads. ISCAS (3) 2005: 2795-2798

Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED 2005: 153-158

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591

Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda: DEPOGIT: dense power-ground interconnect architecture for physical design integrity. ASP-DAC 2004: 517-522

Atsushi Kurokawa, Takashi Sato, Hiroo Masuda: Approximate formulae approach for efficient inductance extraction. ASP-DAC 2003: 143-148

Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto: Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. ASP-DAC 2003: 149-155