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Siew Kei Lam
2010 – today
- 2013
[j17]Bo Liu, Siew Kei Lam, Thambipillai Srikanthan, Weiqi Yuan: Iris Recognition Using Stable Dark Features. JCP 8(1): 41-48 (2013)- [j16]Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan: FPGA-aware techniques for rapid generation of profitable custom instructions. Microprocessors and Microsystems - Embedded Hardware Design 37(3): 259-269 (2013)
- 2012
- [j15]Bo Liu, Siew Kei Lam, Thambipillai Srikanthan, Weiqi Yuan: Iris Recognition of Defocused Images for Mobile phones. IJPRAI 26(8) (2012)
- [c30]Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan: Area-time estimation of C-based functions for design space exploration. FPT 2012: 297-300
- [c29]Yuanbo Zhu, Jigang Wu, Siew Kei Lam, Thambipillai Srikanthan: Reconfiguration Algorithms for Degradable VLSI Arrays with Switch Faults. ICPADS 2012: 356-361
- [c28]Bo Liu, Siew Kei Lam, Thambipillai Srikanthan, Weiqi Yuan: Exploiting stable features for iris recognition of defocused images. ISCAS 2012: 97-100
- [c27]Meiqing Wu, Nirmala Ramakrishnan, Siew Kei Lam, Thambipillai Srikanthan: Low-complexity pruning for accelerating corner detection. ISCAS 2012: 1684-1687
- [c26]Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke: Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. ReCoSoC 2012: 1-8
- 2011
- [j14]Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke: Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs. IEEE Trans. Computers 60(5): 680-692 (2011)
- [c25]Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan: A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. ISVLSI 2011: 278-283
- [c24]Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan: Instruction set customization for area-constrained FPGA designs. SoCC 2011: 329-334
- [c23]Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan: Compiler-assisted technique for rapid performance estimation of FPGA-based processors. SoCC 2011: 341-346
- 2010
- [j13]Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu: Selecting profitable custom instructions for reconfigurable processors. Journal of Systems Architecture - Embedded Systems Design 56(8): 340-351 (2010)
- [c22]Siew Kei Lam, Yun Deng, Jian Hu, Xilong Zhou, Thambipillai Srikanthan: Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations. ARC 2010: 282-293
- [c21]Alok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan: Architecture-Aware Custom Instruction Generation for Reconfigurable Processors. ARC 2010: 414-419
- [c20]Siew Kei Lam, Thambipillai Srikanthan: Accelerating shortest path computations in hardware. CASE 2010: 63-68
- [c19]Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan: Performance estimation framework for FPGA-based processors. FPT 2010: 413-416
- [c18]Song Yang, Siew Kei Lam, Thambipillai Srikanthan: An efficient edge and corner detector. ICARCV 2010: 1628-1631
2000 – 2009
- 2009
- [j12]Siew Kei Lam, Huang Fan, Thambipillai Srikanthan, Wu Jigang: Run-time management of custom instructions on a partially reconfigurable architecture. IJICT 2(1/2): 50-59 (2009)
- [j11]Siew Kei Lam, Thambipillai Srikanthan: Rapid design of area-efficient custom instructions for reconfigurable embedded processing. Journal of Systems Architecture - Embedded Systems Design 55(1): 1-14 (2009)
- [j10]Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke: Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures. IEEE Transactions on Industrial Electronics 56(10): 3998-4005 (2009)
- [c17]Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu: Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection. ACIS-ICIS 2009: 266-270
- [c16]Alok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan: Rapid design exploration framework for application-aware customization of soft core processors. FPL 2009: 539-542
- [c15]Lieu My Chuong, Siew Kei Lam, Thambipillai Srikanthan: Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA. IEEE International Workshop on Rapid System Prototyping 2009: 145-151
- 2008
- [c14]George Rosario Jagadeesh, Siew Kei Lam, Thambipillai Srikanthan: A Short Course on Implementing FPGA Based Digital Systems. ICPADS 2008: 741-744
- 2007
- [j9]Lieu My Chuong, Siew Kei Lam, Thambipillai Srikanthan: Rapid Area-Time Estimation Technique for Porting C-based Applications onto FPGA platforms. Scalable Computing: Practice and Experience 8(4) (2007)
- [c13]Siew Kei Lam, Thambipillai Srikanthan: Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors. ASAP 2007: 89-94
- 2006
- [j8]C. S. Lim, Siew Kei Lam, Hui Tian, Thambipillai Srikanthan: Efficient Architectures for Segmentation of Endoscopic Images in Micro-Robotic Auto Navigation Systems. I. J. Humanoid Robotics 3(4): 523-545 (2006)
- [j7]Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke: Rapid generation of custom instructions using predefined dataflow structures. Microprocessors and Microsystems 30(6): 355-366 (2006)
- [c12]Leipo Yan, Siew Kei Lam, Thambipillai Srikanthan, Wu Jigang: Energy Efficient Cache Tuning with Performance Bound. DELTA 2006: 97-100
- [c11]Siew Kei Lam, Mohammed Shoaib, Thambipillai Srikanthan: Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors. DELTA 2006: 237-242
- [c10]Siew Kei Lam, Bharathi N. Krishnan, Thambipillai Srikanthan: Efficient management of custom instructions for run-time reconfigurable instruction set processors. FPT 2006: 261-264
- 2005
- [j6]Siew Kei Lam, K. Sridharan, Thambipillai Srikanthan: VLSI-efficient schemes for high-speed construction of tangent graph. Robotics and Autonomous Systems 51(4): 248-260 (2005)
- [c9]Siew Kei Lam, Yun Deng, Thambipillai Srikanthan: Morphable Structures for Reconfigurable Instruction Set Processors. Asia-Pacific Computer Systems Architecture Conference 2005: 450-463
- 2004
- [j5]Thambipillai Srikanthan, Siew Kei Lam, Mishra Suman: Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System. IEEE Trans. Computers 53(1): 69-72 (2004)
- [c8]Suchitra Sathyanarayana, Siew Kei Lam, Thambipillai Srikanthan: High-throughput image rotation using sign-prediction based redundant cordic algorithm. ICIP 2004: 2833-2836
- 2003
- [c7]Hui Tian, Siew Kei Lam, Thambipillai Srikanthan: Implementing Otsu's thresholding process using area-time efficient logarithmic approximation unit. ISCAS (4) 2003: 21-24
- [c6]Siew Kei Lam, Devendra K. Chaudhaiy, Thambipillai Srikanthan: Low cost logarithmic techniques for high-precision computations. ISCAS (5) 2003: 125-128
- [c5]K. H. Quek, Siew Kei Lam, N. K. Agrawal, Thambipillai Srikanthan: Architectural design and analysis toolbox to implement shortest path algorithms in hardware. ISCAS (3) 2003: 224-227
- 2002
- [j4]Siew Kei Lam, Thambipillai Srikanthan: Environment Modelling for Robot Navigation Using VLSI-Efficient Logarithmic Approximation Method. Journal of Intelligent and Robotic Systems 35(1): 23-40 (2002)
- [j3]Siew Kei Lam, Thambipillai Srikanthan: A linear approximation based hybrid approach for binary logarithmic conversion. Microprocessors and Microsystems 26(8): 353-361 (2002)
- [c4]C. S. Lim, Thambipillai Srikanthan, Vijayan K. Asari, Siew Kei Lam: Fuzzy-ART based image compression for hardware implementation. APCCAS (2) 2002: 147-150
- [c3]Siew Kei Lam, Thambipillai Srikanthan, N. Goyal, N. Tyagi: Incorporating area-time flexibility to a binary signed-digit adder. APCCAS (1) 2002: 485-489
- [c2]Hui Tian, Siew Kei Lam, Thambipillai Srikanthan, Chip-Hong Chang: An efficient architecture for adaptive progressive thresholding. APCCAS (1) 2002: 513-516
- [c1]Hui Tian, Thambipillai Srikanthan, Vijayan K. Asari, Siew Kei Lam: Study on the Effect of Object to Camera Distance on Polynomial Expansion Coefficients in Barrel Distortion Correction. SSIAI 2002: 255-259
- 2001
- [j2]Siew Kei Lam, Thambipillai Srikanthan: High-Speed Environment Representation Scheme for Dynamic Path Planning. Journal of Intelligent and Robotic Systems 32(3): 307-319 (2001)
- 2000
- [j1]Siew Kei Lam, Thambipillai Srikanthan: Dynamic multicast routing in VLSI. Computer Communications 23(11): 1055-1063 (2000)
Coauthor Index
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last updated on 2013-04-12 20:31 CEST by the dblp team