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 | 2013 | |
|---|---|---|
| i1 |      | Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, M. Irfan Uddin, Chris R. Jesshope: MGSim - Simulation tools for multi-core processor architectures. CoRR abs/1302.1390 (2013) |
| 2012 | ||
| c3 | | Raphaël Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope: Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. DSD 2012: 501-508 |
| 2009 | ||
| j3 | | Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp: Implementation and evaluation of a microthread architecture. Journal of Systems Architecture - Embedded Systems Design 55(3): 149-161 (2009) |
| j2 | | Michiel W. van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra: An implementation of the SANE Virtual Processor using POSIX threads. Journal of Systems Architecture - Embedded Systems Design 55(3): 162-169 (2009) |
| j1 | | Chris R. Jesshope, Mike Lankamp, Li Zhang: The implementation of an SVP many-core processor and the evaluation of its memory architecture. SIGARCH Computer Architecture News 37(2): 38-45 (2009) |
| c2 | | Chris R. Jesshope, Mike Lankamp, Li Zhang: Evaluating CMPs and Their Memory Architecture. ARCS 2009: 246-257 |
| 2008 | ||
| c1 | | Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang: A general model of concurrency and its implementation as many-core dynamic RISC processors. ICSAMOS 2008: 1-9 |
| 1 | Thomas A. M. Bernard | |
| 2 | Kostas Bousias | |
| 3 | Jian Fu | |
| 4 | Liang Guang | |
| 5 | Chris R. Jesshope | |
| 6 | Simon Polstra | |
| 7 | Raphael 'kena' Poss (Raphaël Poss) | |
| 8 | Michiel W. van Tol | |
| 9 | M. Irfan Uddin | |
| 10 | Qiang Yang 0006 | |
| 11 | Li Zhang |
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