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 | 2012 | |
|---|---|---|
| j16 |      | Ashwini Jeggari, Debora S. Marks, Erik Larsson: miRcode: a map of putative microRNA target sites in the long non-coding transcriptome. Bioinformatics 28(15): 2062-2063 (2012) |
| j15 | | Farrokh Ghani Zadegan, Urban Ingelsson, Erik Larsson, Gunnar Carlsson: Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687. IEEE Design & Test of Computers 29(2): 79-88 (2012) |
| j14 | | Breeta SenGupta, Urban Ingelsson, Erik Larsson: Scheduling Tests for 3D Stacked Chips under Power Constraints. J. Electronic Testing 28(1): 121-135 (2012) |
| j13 | | Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson: Access Time Analysis for IEEE P1687. IEEE Trans. Computers 61(10): 1459-1472 (2012) |
| c50 | | Erik Larsson, Farrokh Ghani Zadegan: Accessing Embedded DfT Instruments with IEEE P1687. ATS 2012: 71-76 |
| c49 | | Erik Larsson, Konstantin Sibin: Fault management in an IEEE P1687 (IJTAG) environment. DDECS 2012: 7 |
| c48 | | Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson: Re-using chip level DFT at board level. European Test Symposium 2012: 1 |
| c47 | | Sairamesh Nammi, Bo Göransson, Erik Larsson, Qingyu Miao: Design principles for four branch downlink MIMO for long term HSPA evolution. ICC 2012: 6051-6055 |
| c46 | | Breeta SenGupta, Urban Ingelsson, Erik Larsson: Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. VLSI Design 2012: 442-447 |
| 2011 | ||
| c45 | | Farrokh Ghani Zadegan, Urban Ingelsson, Golnaz Asani, Gunnar Carlsson, Erik Larsson: Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints. Asian Test Symposium 2011: 525-531 |
| c44 | | Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson: Design automation for IEEE P1687. DATE 2011: 1412-1417 |
| c43 | | Urban Ingelsson, Shih-Yen Chang, Erik Larsson: Measurement point selection for in-operation wear-out monitoring. DDECS 2011: 381-386 |
| c42 | | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson: Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. ICCD 2011: 419-426 |
| 2010 | ||
| c41 | | Mudassar Majeed, Daniel Ahlstrom, Urban Ingelsson, Gunnar Carlsson, Erik Larsson: Efficient Embedding of Deterministic Test Data. Asian Test Symposium 2010: 159-162 |
| c40 | | Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson: Test Time Analysis for IEEE P1687. Asian Test Symposium 2010: 455-460 |
| c39 | | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson: Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. DATE 2010: 1572-1577 |
| c38 | | Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson: Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. DELTA 2010: 281-285 |
| c37 | | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson: Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. DSN 2010: 121-130 |
| c36 | | Erik Larsson, Bart Vermeulen, Kees Goossens: A distributed architecture to check global properties for post-silicon debug. European Test Symposium 2010: 182-187 |
| c35 | | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara: Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. European Test Symposium 2010: 259 |
| c34 | | N. S. Vinay, Indira Rawaty, Erik Larsson, M. S. Gaur, Virendra Singh: Thermal aware test scheduling for stacked multi-chip-modules. EWDTS 2010: 343-349 |
| c33 | | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara: Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI 2010: 73-78 |
| c32 | | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson: Energy-efficient redundant execution for chip multiprocessors. ACM Great Lakes Symposium on VLSI 2010: 143-146 |
| 2009 | ||
| c31 | | Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson: On Scan Chain Diagnosis for Intermittent Faults. Asian Test Symposium 2009: 47-54 |
| c30 | | Mikael Väyrynen, Virendra Singh, Erik Larsson: Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. DATE 2009: 484-489 |
| c29 | | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal: On Minimization of Peak Power for Scan Circuit during Test. European Test Symposium 2009: 25-30 |
| 2008 | ||
| j12 | | Erik Larsson, Zebo Peng: A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling. J. Electronic Testing 24(5): 497-504 (2008) |
| j11 | | Erik Larsson: Architecture for integrated test data compression and abort-on-fail testing in a multi-site environment. IET Computers & Digital Techniques 2(4): 275-284 (2008) |
| j10 | | Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng: Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 973-977 (2008) |
| c28 | | Anders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Eles, Zebo Peng: Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. DATE 2008: 188-193 |
| c27 | | Anders Larsson, Xin Zhang, Erik Larsson, Krishnendu Chakrabarty: SOC Test Optimization with Compression-Technique Selection. ITC 2008: 1 |
| 2007 | ||
| j9 | | Erik Larsson, Per Lindahl, Petter Mostad: HeliCis: a DNA motif discovery tool for colocalized motif pairs with periodic spacing. BMC Bioinformatics 8 (2007) |
| j8 | | Erik Larsson, Stina Edbom: Test data truncation for test quality maximisation under ATE memory depth constraint. IET Computers & Digital Techniques 1(1): 27-37 (2007) |
| c26 | | Erik Larsson, Jon Persson: An Architecture for Combined Test Data Compression and Abort-on-Fail Test. ASP-DAC 2007: 726-731 |
| c25 | | Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng: Optimized integration of test compression and sharing for SOC testing. DATE 2007: 207-212 |
| c24 | | Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters: Test quality analysis and improvement for an embedded asynchronous FIFO. DATE 2007: 859-864 |
| c23 |  | Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng: A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing. DDECS 2007: 61-66 |
| c22 | | Gunnar Carlsson, Johan Holmqvist, Erik Larsson: Protocol requirements in an SJTAG/IJTAG environment. ITC 2007: 1-9 |
| c21 | | Erik Larsson, Mehdi Amirijoo, Daniel Karlsson, Petru Eles: What impacts course evaluation? ITiCSE 2007: 333 |
| 2006 | ||
| j7 | | Erik Larsson, Zebo Peng: Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process. IEEE Trans. Computers 55(2): 227-239 (2006) |
| j6 | | Erik Larsson, Hideo Fujiwara: System-on-chip test scheduling with reconfigurable core wrappers. IEEE Trans. VLSI Syst. 14(3): 305-309 (2006) |
| c20 | | Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng: Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling. ITC 2006: 1-10 |
| 2005 | ||
| j5 | | Julien Pouget, Erik Larsson, Zebo Peng: Multiple-Constraint Driven System-on-Chip Test Time Optimization. J. Electronic Testing 21(6): 599-611 (2005) |
| j4 | | Erik Larsson, Julien Pouget, Zebo Peng: Abort-on-Fail Based Test Scheduling. J. Electronic Testing 21(6): 651-658 (2005) |
| c19 | | Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng: SOC Test Scheduling with Test Set Sharing and Broadcasting. Asian Test Symposium 2005: 162-169 |
| c18 | | Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng: Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip. DSD 2005: 403-411 |
| c17 | | David Bäckström, Gunnar Carlsson, Erik Larsson: Remote boundary-scan system test control for the ATCA standard. ITC 2005: 10 |
| c16 | | Erik Larsson, Stina Edbom: Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint. VLSI-SoC 2005: 221-244 |
| 2004 | ||
| j3 | | Erik Larsson, Hideo Fujiwara: Preemptive System-on-Chip Test Scheduling. IEICE Transactions 87-D(3): 620-629 (2004) |
| j2 | | Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng: Efficient test solutions for core-based designs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 758-775 (2004) |
| c15 | | Stina Edbom, Erik Larsson: An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint. Asian Test Symposium 2004: 254-257 |
| c14 | | |
| c13 | | Erik Larsson, Anders Larsson: Student-oriented examination in a computer architecture course. ITiCSE 2004: 245 |
| c12 | | |
| 2003 | ||
| c11 | | Erik Larsson, Hideo Fujiwara: Optimal System-on-Chip Test Scheduling. Asian Test Symposium 2003: 306-311 |
| c10 | | Julien Pouget, Erik Larsson, Zebo Peng: SOC Test Time Minimization Under Multiple Constraints. Asian Test Symposium 2003: 312-317 |
| c9 | | Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng: Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip. DFT 2003: 385-392 |
| c8 | | |
| c7 | | Erik Larsson, Hideo Fujiwara: Test Resource Partitioning and Optimization for SOC Designs. VTS 2003: 319-324 |
| 2002 | ||
| j1 | | Erik Larsson, Zebo Peng: An Integrated Framework for the Design and Optimization of SOC Test Solutions. J. Electronic Testing 18(4-5): 385-400 (2002) |
| c6 | | Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng: Integrated Test Scheduling, Test Parallelization and TAMDesign. Asian Test Symposium 2002: 397-404 |
| 2001 | ||
| c5 | | Erik Larsson, Zebo Peng: Test Scheduling and Scan-Chain Division under Power Constraint. Asian Test Symposium 2001: 259-264 |
| c4 | | |
| c3 | | Erik Larsson, Zebo Peng, Gunnar Carlsson: The Design and Optimization of SOC Test Solutions. ICCAD 2001: 523-530 |
| 2000 | ||
| c2 | | John Saul, Betsy Black, Erik Larsson: Helpdesk.Drew.Edu: Home Growing a Helpdesk Solution Using Open-Source Technology. SIGUCCS 2000: 289-293 |
| 1997 | ||
| c1 | | Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo Peng: A controller testability analysis and enhancement technique. ED&TC 1997: 153-157 |
Colors in the list of coauthors
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