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K. T. Lau
2000 – 2009
- 2008
[j5]S. Ramakrishnan, K. T. Lau: Improved Dynamic Current Mode Logic for Low Power Applications. Journal of Circuits, Systems, and Computers 17(2): 183-190 (2008)
[j4]W. J. Yang, Y. Zhou, K. T. Lau: Low Power Adiabatic Programmable Logic Array with Single Clock Iapdl. Journal of Circuits, Systems, and Computers 17(2): 211-219 (2008)- 2002
[j3]H. H. Wong, K. T. Lau: Low Power 16 x 16 Bit Multiplier Design Using PAL-2N Logic Family. Journal of Circuits, Systems, and Computers 11(2): 155-164 (2002)- 2000
[j2]K. W. Ng, K. T. Lau: A Novel Adiabatic Register File Design. Journal of Circuits, Systems, and Computers 10(1-2): 67-76 (2000)
1990 – 1999
- 1999
[j1]K. W. Ng, K. T. Lau: An Adiabatic 4: 2 Compressor Design for Low Power VLSI. Journal of Circuits, Systems, and Computers 9(5-6): 339-346 (1999)
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last updated on 2012-12-02 22:06 CET by the dblp team



