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 | 2013 | |
|---|---|---|
| j4 |      | Hyuk-Jun Lee, Seung-Chul Kim, Eui-Young Chung: A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method. IEICE Transactions 96-D(4): 963-966 (2013) |
| 2008 | ||
| j3 | | Hyuk-Jun Lee, Eui-Young Chung: Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory. IEEE Trans. VLSI Syst. 16(3): 289-301 (2008) |
| 2007 | ||
| j2 | | Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, Eui-Young Chung: Latency-Aware Bus Arbitration for Real-Time Embedded Systems. IEICE Transactions 90-D(3): 676-679 (2007) |
| j1 | | Eui-Young Chung, Hyuk-Jun Lee, Sung Woo Chung: Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis. IEICE Transactions 90-A(4): 875-878 (2007) |
| c3 | | Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, Naehyuck Chang, Eui-Young Chung: Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems. ASP-DAC 2007: 159-164 |
| 2000 | ||
| c2 | | Hyuk-Jun Lee, Michael J. Flynn: Coarse-grained carry architecture for FPGA (poster abstract). FPGA 2000: 217 |
| c1 |  | Hyuk-Jun Lee, Albert A. Liddicoat, Michael J. Flynn: Exploiting Parallelism and Data Locality of Systolic Array Applications using Multi-Ported FPGA. PDPTA 2000 |
| 1 | Kwanhu Bang | |
| 2 | Naehyuck Chang | |
| 3 | Eui-Young Chung | |
| 4 | Sung Woo Chung | |
| 5 | Michael J. Flynn | |
| 6 | Minje Jun | |
| 7 | Seung-Chul Kim | |
| 8 | Albert A. Liddicoat |
Colors in the list of coauthors
Last update Sat May 25 19:53:45 2013 CET by the DBLP Team —
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