Yung-Pin Lee

Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. J. Solid-State Circuits 46(8): 1893-1903 (2011)

Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu: A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC 2011: 713-718

Cihun-Siyong Alex Gong, Tim K. Shia, Yung-Pin Lee, Bo-Wei Chen, Kai-Wen Yao, Muh-Tian Shiue: CMOS comparator for medical imaging. BMEI 2011: 1060-1063

Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai: A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. European Test Symposium 2011: 39-44

Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. CICC 2010: 1-4

Ji-Eun Jang, Yung-Kuang Miao, Yung-Pin Lee: High-bandwidth power-scalable 10-bit pipelined ADC using bandwidth-reconfigurable operational amplifier. ISCAS 2010: 4029-4032

Kuan-Yu Lin, Ji-Eun Jang, Ching-Hsuan Hsieh, Yung-Pin Lee: A pipelined analog-to-digital converter using incomplete-settling-without-slewing technique. ISCAS 2010: 4037-4040

Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. ISSCC 2009: 82-83

Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee: Subharmonically injection-locked PLLs for ultra-low-noise clock generation. ISSCC 2009: 92-93

Chung-Wei Lin, Yung-Pin Lee, Wen-Tsao Chen: A 1.5 bit 5^th order CT/DT delta sigma class D amplifier with power efficiency improvement. ISCAS 2008: 280-283

Huan-Jen Yang, Ke-Horng Chen, Yung-Pin Lee: Feed-Forward Pulse Width Modulation for High Line Regulation Buck or Boost Converters. ISCAS 2007: 785-788

Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung-Wei Ku: A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm. ASP-DAC 1998: 145-150

Yung-Pin Lee, Thou-Ho Chen, Liang-Gee Chen, Mei-Juan Chen, Chung-Wei Ku: A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method. IEEE Trans. Circuits Syst. Video Techn. 7(3): 459-467 (1997)

Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee: A flexible data-interlacing architecture for full-search block-matching algorithm. ASAP 1997: 96-

Chung-Wei Ku, Liang-Gee Chen, You-Ming Chiu, Yung-Pin Lee: A pseudo-object-oriented very low bit-rate video coding system with cache VQ for detail compensation. ICIP (1) 1996: 653-656

Mei-Juan Chen, Liang-Gee Chen, Tzi-Dar Chiueh, Yung-Pin Lee: A new block-matching criterion for motion estimation and its implementation. IEEE Trans. Circuits Syst. Video Techn. 5(3): 231-236 (1995)