Guy Lemieux

Guy G. Lemieux, Guy G. F. Lemieux

University of British Columbia

	2012
j8		David Grant, Graeme Smecher, Guy G. F. Lemieux, Rosemary Francis: Rapid Synthesis and Simulation of Computational Circuits in an MPPA. Signal Processing Systems 67(1): 47-63 (2012)
c44		Alexander Brant, Guy G. F. Lemieux: ZUMA: An Open FPGA Overlay Architecture. FCCM 2012: 93-96
c43		Aaron Severance, Guy Lemieux: VENICE: A Compact Vector Processor for FPGA Applications. FCCM 2012: 245
c42		Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux: Accelerator compiler for the VENICE vector processor. FPGA 2012: 229-232
c41		Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk: Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264
c40		Chris C. Wang, Guy G. F. Lemieux: Parallel FPGA placement based on individual LUT placement (abstract only). FPGA 2012: 269
c39		Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk: Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. FPL 2012: 91-98
c38		Alexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G. F. Lemieux: Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew. FPT 2012: 235-238
c37		Aaron Severance, Guy Lemieux: VENICE: A compact vector processor for FPGA applications. FPT 2012: 261-268
	2011
j7		Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton: Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. VLSI Syst. 19(12): 2195-2208 (2011)
c36		Jonathan Rose, Guy G. Lemieux: The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. FPGA 2011: 1-2
c35		Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux: VEGAS: soft vector processor with scratchpad memory. FPGA 2011: 15-24
c34		David Grant, Chris Wang, Guy G. Lemieux: A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. FPGA 2011: 123-132
c33		Chris C. Wang, Guy G. Lemieux: Scalable and deterministic timing-driven parallel placement for FPGAs. FPGA 2011: 153-162
c32		Ameer Abdelhadi, Guy G. F. Lemieux: Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations. ReConFig 2011: 20-26
c31		Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton: Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig 2011: 41-48
	2010
j6		Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William G. Dunford, Patrick R. Palmer: A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid. IEEE Trans. on Circuits and Systems 57-I(8): 2099-2108 (2010)
c30		Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton: The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA 2010: 263-272
	2009
j5		Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux: Vector Processing as a Soft Processor Accelerator. TRETS 2(2) (2009)
c29		Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet: Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA 2009: 43-52
c28		Johnny Tsung Lin Ho, Guy G. Lemieux: PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. FPGA 2009: 257-260
c27		David Leong, Guy G. Lemieux: Replace: An incremental placement algorithm for field programmable gate arrays. FPL 2009: 154-161
c26		Xiao Dong, Guy G. F. Lemieux: PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess. FPT 2009: 88-95
c25		David Grant, Graeme Smecher, Guy Lemieux, Rosemary Francis: Rapid synthesis and simulation of computational circuits in an MPPA. FPT 2009: 151-158
c24		Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet: Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. NOCS 2009: 234-243
	2008
j4		David Grant, Guy G. Lemieux: Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. TRETS 1(3) (2008)
j3		Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. VLSI Syst. 16(11): 1521-1534 (2008)
j2		Edmund Lee, Guy Lemieux, Shahriar Mirabbasi: Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. Signal Processing Systems 51(1): 57-76 (2008)
c23		Guy G. Lemieux, Tarek A. El-Ghazawi: Designing with extreme parallelism. FPGA 2008: 1-2
c22		Tarek A. El-Ghazawi, Guy G. Lemieux: Extreme parallel architectures for the masses. FPGA 2008: 127-128
c21		Jason Yu, Guy G. Lemieux, Christopher Eagleston: Vector processing as a soft-core CPU accelerator. FPGA 2008: 222-232
c20		Johnny Tsung Lin Ho, Guy G. F. Lemieux: PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters. FPT 2008: 73-80
c19		Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William G. Dunford, Patrick R. Palmer: Energy Recovery from High-Frequency Clocks Using DC-DC Converters. ISVLSI 2008: 162-167
	2007
j1		Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux: A Survey and Taxonomy of GALS Design Styles. IEEE Design & Test of Computers 24(5): 418-428 (2007)
c18		Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165
c17		Jason Yu, Guy Lemieux: A Case for Soft Vector Processors in FPGAs. FPT 2007: 341-344
c16		David Yeager, Darius Chiu, Guy G. Lemieux: Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. SLIP 2007: 33-40
	2006
c15		David Grant, Scott Chin, Guy G. Lemieux: Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. FPL 2006: 1-4
c14		Edmund Lee, Guy Lemieux, Shahriar Mirabbasi: Interconnect driver design for long wires in field-programmable gate arrays. FPT 2006: 89-96
c13		David Grant, Guy Lemieux: Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route. FPT 2006: 189-196
c12		Marvin Tom, David Leong, Guy G. Lemieux: Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ICCAD 2006: 680-687
	2005
c11		Marvin Tom, Guy G. Lemieux: Logic block clustering of large designs for channel-width constrained FPGAs. DAC 2005: 726-731
c10		Anthony J. Yu, Guy G. Lemieux: Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. FPL 2005: 255-262
c9		Anthony J. Yu, Guy G. Lemieux: FPGA Defect Tolerance: Impact of Granularity. FPT 2005: 189-196
	2004
b1		Guy Lemieux, David A. Lewis: Design of interconnection networks for programmable logic. Kluwer 2004, isbn 978-1-4020-7700-5, pp. I-XX, 1-206
c8		Guy Lemieux, Edmund Lee, Marvin Tom, Anthony J. Yu: Directional and single-driver wires in FPGA interconnect. FPT 2004: 41-48
	2002
c7		Guy G. Lemieux, David M. Lewis: Circuit design of routing switches. FPGA 2002: 19-28
c6		Guy G. Lemieux, David M. Lewis: Analytical Framework for Switch Block Design. FPL 2002: 122-131
	2001
c5		Guy G. Lemieux, David M. Lewis: Using sparse crossbars within LUT. FPGA 2001: 59-68
	2000
c4		Guy G. Lemieux, Paul Leventis, David M. Lewis: Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164
c3		R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
	1998
c2		A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
	1997
c1		Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic: On two-step routing for FPGAS. ISPD 1997: 60-66

Coauthor Index

Colors in the list of coauthors

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